AD9740ARU Analog Devices Inc, AD9740ARU Datasheet - Page 18

• Manufacturer Part Number: AD9740ARU
• Description: IC DAC 10BIT 210MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9740ARU

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 145mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• For Use With: AD9740ACP-PCBZ - BOARD EVAL FOR AD9740ACP

AD9740
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (that is, V
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9740. A
differential resistor, R
the output of the transformer is connected to the load, R
via a passive reconstruction filter or cable. R
by the transformer’s impedance ratio and provides the proper
source termination that results in a low VSWR. Note that
approximately half the signal power is dissipated across R
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-
ended conversion, as shown in Figure 33. The AD9740 is
configured with two equal load resistors, R
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the
differential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
off a dual supply because its output is approximately ±1 V. A
high speed amplifier capable of preserving the differential
performance of the AD9740 while meeting other system level
objectives (that is, cost or power) should be selected. The op
amp’s differential gain, gain setting resistor values, and full-scale
output swing capabilities should all be considered when
optimizing this circuit.
The differential circuit shown in Figure 34 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9740 and the op amp, is also used to level shift the
differential output of the AD9740 to midsupply (that is,
AVDD/2). The AD8041 is a suitable op amp for this application.
AD9740
IOUTA
IOUTB
Figure 33. DC Differential Coupling Using an Op Amp
22
21
25Ω
DIFF
C
, can be inserted in applications where
OPT
25Ω
225Ω
225Ω
LOAD
OUTA
DIFF
500Ω
, of 25 Ω. The
is determined
and V
AD8047
500Ω
OUTB
DIFF
LOAD
.
)
B
,
Rev. B | Page 18 of 32
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 35 shows the AD9740 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly
terminated 50 Ω cable because the nominal full-scale current,
I
In this case, R
by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
Different values of I
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL),
discussed in the Analog Outputs section. For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 36 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9740 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the Analog
Outputs section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates can be
limited by U1’s slew rate capabilities. U1 provides a negative
unipolar output voltage, and its full-scale output voltage is
simply the product of R
should be set within U1’s voltage output swing capabilities by
scaling I
performance can result with a reduced I
required to sink less signal current.
OUTFS
AD9740
AD9740
, of 20 mA flows through the equivalent R
IOUTA
IOUTB
IOUTA
IOUTB
OUTFS
Figure 34. Single-Supply DC Differential Coupled Circuit
Figure 35. 0 V to 0.5 V Unbuffered Voltage Output
22
21
and/or R
LOAD
22
21
25Ω
I
OUTFS
represents the equivalent load resistance seen
OUTFS
C
OPT
FB
25Ω
= 20mA
FB
. An improvement in ac distortion
and R
and I
25Ω
LOAD
OUTFS
225Ω
225Ω
50Ω
can be selected as long as
. The full-scale output
1kΩ
OUTFS
AD8041
500Ω
because U1 is
V
OUTA
LOAD
1kΩ
50Ω
= 0V TO 0.5V
of 25 Ω.
LOAD
AVDD
.