AD420ARZ-32 Analog Devices Inc, AD420ARZ-32 Datasheet - Page 7

• Manufacturer Part Number: AD420ARZ-32
• Description: IC DAC SRL 16BIT 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD420ARZ-32

• Data Interface: Serial
• Settling Time: 2.5µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 176mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 400SPS
• Input Channel Type: Serial
• Supply Current: 4.2mA
• Digital Ic Case Style: SOIC
• No. Of Pins: 24
• Number Of Channels: 1
• Resolution: 16b
• Conversion Rate: 0.4KSPS
• Interface Type: SERIAL 3W SPI UW
• Single Supply Voltage (typ): 15/18/24V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Delta-Sigma
• Power Supply Requirement: Single
• Output Type: Current/Voltage
• Integral Nonlinearity Error: ±0.012LSB
• Single Supply Voltage (min): 12V
• Single Supply Voltage (max): 32V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DATA OUT
DATA OUT
TIMING REQUIREMENTS
T
THREE-WIRE INTERFACE
Table 5. Timing Specification for 3-Wire Interface
Parameter
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
Serial Output Delay Time
Clear Pulse Width
THREE-WIRE INTERFACE FAST EDGES ON DIGITAL
INPUT
With a fast rising edge (<10 ns) on one of the serial inputs
(CLOCK, DATA IN, LATCH) while another input is logic high,
the part may be triggered into a test mode and the contents of
the data register may become corrupted, which may result in
the output being loaded with an incorrect value. If fast edges are
expected on the digital input lines, it is recommended that the
latch line remain at Logic 0 during serial loading of the DAC.
Similarly, the clock line should remain low during updates of
the DAC via the latch pin. Alternatively, the addition of small
value capacitors on the digital lines will slow down the edge.
A
DATA IN
DATA IN
CLOCK
CLOCK
LATCH
LATCH
= −40°C to +85°C, V
Figure 3. Timing Diagram for 3-Wire Interface
1 0 1 1 0 0 1
t
t
CL
DS
CC
t
DW
WORD “N – 1”
t
WORD “N”
CK
= +12 V to +32 V.
t
DH
0 0
t
CH
t
1 1 1 0 0
LD
Label
t
t
t
t
t
t
t
t
t
t
t
CK
CL
CH
DW
DS
DH
LD
LL
LH
SD
CLR
t
LL
t
SD
Limit
125
80
80
225
300
80
80
40
5
80
50
1 1
t
LH
1
WORD “N + 1”
1
WORD “N”
0
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
0 0
1
1
1
Rev. H | Page 7 of 16
Table 6. Timing Specifications for Asynchronous Interface
Parameter
Asynchronous Clock Period
Asynchronous Clock Low Time
Asynchronous Clock High Time
Data Stable Width (Critical Clock Edge)
Data Setup Time (Critical Clock Edge)
Data Hold Time (Critical Clock Edge)
Clear Pulse Width
ASYNCHRONOUS INTERFACE
Note that in the timing diagram for asynchronous mode oper-
ation each data word is framed by a START (0) bit and a STOP
(1) bit. The data timing is with respect to the rising edge of the
CLOCK at the center of each bit cell. Bit cells are 16 clocks
long, and the first cell (the START bit) begins at the first clock
following the leading (falling) edge of the START bit. Thus, the
MSB (D15) is sampled 24 clock cycles after the beginning of
the START bit, D14 is sampled at clock number 40, and so on.
During any dead time before writing the next word the DATA
IN pin must remain at Logic 1.
The DAC output updates when the STOP bit is received. In
the case of a framing error (the STOP bit sampled as a 0) the
AD420 will output a pulse at the DATA OUT pin one clock
period wide during the clock period subsequent to sampling
the STOP bit. The DAC output will not update if a framing
error is detected.
DATA IN
DATA IN
DATA IN
CLOCK
CLOCK
CLOCK
(INTERNALLY GENERATED LATCH)
Figure 4. Timing Diagram for Asynchronous Interface
CLOCK COUNTER STARTS HERE
EXPANDED TIME VIEW BELOW
0 1 2
0
START BIT
CONFIRM START BIT
8
1
t
t
ADS
ACL
EXPANDED TIME VIEW BELOW
t
t
ADW
ACK
0
16
t
t
ACH
ADH
DATA BIT 15
Label
t
t
t
t
t
t
t
ACK
ACL
ACH
ADW
ADS
ADH
CLR
24
SAMPLE BIT 15
0
Limit
400
50
150
300
60
20
50
1
AD420
BIT 14
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min