PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 27

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2
to this value, whenever the standard configuration is selected.
As can be seen there the beginning of a input time-slot is defined such, that the input
lines have settled to a stable value, when the datum is actually sampled.
4096- and 8192-kbit/s data is sampled in the middle of the bit period at the falling edge
of the respective data clock. 2048-kbit/s data is sampled after 3/4 of the according bit
period, i.e. with the rising edge of the 4
In the primary access configuration a different timing scheme may apply to the odd
physical input lines. They are affected by the content of the clock shift register (CSR),
which can be programmed via the P interface (see chapter 2.2).
The clock shift register holds the information, how the frame structure is shifted in the
primary access configuration. Its content defaults to 00
Semiconductor Group
nd
4096-kHz clock cycle of the considered bit period.
th
8192-kHz clock cycle or the falling edge of the
27
H
after power up and is also set
Functional Description
PEB 2445
02.96