PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 45

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.2
Access in the multiplexed P-interface mode:
Access in the demultiplexed P-interface mode:
X
B
Z
VN (3:0) Version Number according to the table below:
VN3
1
1
4.3
Access in the multiplexed P-interface mode:
Access in the demultiplexed P-interface mode:
Reset value: 00
X
IR
COV
CN4
Semiconductor Group
CN0
Status Register (STA)
Conference Status Register (CST)
AD7
AD7
don’t care
Busy: The chip is busy resetting the connection memory (B = 1). B is
undefined after power up and logical 0 after the device initialization. The three
byte indirect access register is not accessible.
Note: The maximum time for resetting is 250 s.
Incomplete instruction; a three byte indirect instruction is not completed
(Z = 1). Z is 0 after power up.
Note: Z is reset and the indirect access is cancelled by setting MOD:RI or
B
X
don’t care
Initialization Request. The connection memory and the conference
control memory may have lost data (IR = 1). The IR bit is set after power
failure or inappropriate clocking and is reset by reading CST.
Conference Overflow (overflow
Conference Number of the conference in overflow
H
VN2
0
0
resetting MOD:RC.
IR
Z
COV
X
VN1
0
0
CN4
X
45
CN3
VN3
VN0
0
1
logical 1)
CN2
VN2
Read, address: 0
Read, address: 0
Read, address: 4
Read, address: 2
Detailed Register Description
Device Versions
A1
V 1.2
CN1
VN1
AD0
AD0
CN0
VN0
H
H
H
H
PEB 2445
02.96