AD9779BSVZ Analog Devices Inc, AD9779BSVZ Datasheet
AD9779BSVZ
Specifications of AD9779BSVZ
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AD9779BSVZ Summary of contents
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FEATURES Low power: 1 GSPS, 600 mW @ 500 MSPS, full operating conditions SFDR = 78 dBc 100 MHz OUT Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF Analog output: adjustable ...
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AD9776/AD9778/AD9779 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Digital Specifications ................................................................... 6 ...
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FUNCTIONAL BLOCK DIAGRAM DELAY SYNC_O LINE SYNC_I DELAY DATACLK_OUT LINE DATA ASSEMBLER I P1D(15:0) LATCH Q LATCH P2D(15:0) CLOCK GENERATION/DISTRIBUTION 2× 2× 2× × /8 DAC ... 7 2× 2× 2× DIGITAL CONTROLLER ...
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AD9776/AD9778/AD9779 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, MIN MAX otherwise noted. Table 1. AD9776, AD9778, and AD9779 DC Specifications Parameter Min RESOLUTION ACCURACY Differential ...
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Parameter Min 8× Mode Modulation, DAC GSPS 262.5 MHz DAC Power-Down Mode Power Supply Rejection Ratio, −0.3 AVDD33 OPERATING RANGE −40 1 Based kΩ external resistor. AD9776 AD9778 Typ Max ...
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AD9776/AD9778/AD9779 DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless ...
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DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications Parameter INPUT DATA (ALL MODES, −40°C to +85°C) Set-Up Time, Input Data to DATACLK Hold Time, Input Data to DATACLK Set-Up Time, Input Data ...
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AD9776/AD9778/AD9779 ABSOLUTE MAXIMUM RATINGS Table 5. With Respect Parameter To Rating AVDD33, DVDD33 AGND, −0 +3.6 V DGND, CGND DVDD18, CVDD18 AGND, −0 +1.98 V DGND, CGND AGND DGND, −0 +0.3 V CGND DGND ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 ...
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AD9776/AD9778/AD9779 Pin No. Mnemonic Description 39 TXENABLE Transmit Enable. 40 P2D<11> Port 2, Data Input D11 (MSB). 41 P2D<10> Port 2, Data Input D10. 42 P2D<9> Port 2, Data Input D9. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital ...
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CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 CLK+ 5 CLK– 6 CGND ...
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AD9776/AD9778/AD9779 Pin No. Mnemonic Description 41 P2D<12> Port 2, Data Input D12. 42 P2D<11> Port 2, Data Input D11. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<10> Port 2, Data Input D10. 46 P2D<9> Port 2, ...
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CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 CLK+ 5 CLK– 6 CGND ...
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AD9776/AD9778/AD9779 Pin No. Mnemonic Description 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<12> Port 2, Data Input D12. 46 P2D<11> Port 2, Data Input D11. 47 P2D<10> Port 2, Data Input D10. 48 P2D<9> Port 2, ...
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TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 –3 –4 –5 –6 0 10k 20k 30k 40k CODE Figure 6. AD9779 Typical INL 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 10k 20k 30k 40k CODE Figure ...
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AD9776/AD9778/AD9779 100 160MSPS DATA 200MSPS DATA (MHz) OUT Figure 12. AD9779 Out-of-Band SFDR vs. f 100 150MSPS DATA 100MSPS ...
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DATA f = 200MSPS 90 DATA 250MSPS DATA (MHz) OUT Figure 18. AD9779 Third-Order IMD vs 1× Interpolation OUT 100 f = ...
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AD9776/AD9778/AD9779 100 95 90 0dBFS 85 –3dBFS 80 75 –6dBFS 120 160 200 240 f (MHz) OUT Figure 24. IMD Performance vs. Digital Full-Scale Input, 4× Interpolation 200 MSPS DATA ...
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DAC –158 f DAC –162 f = 800MSPS DAC –166 –170 (MHz) OUT Figure 30. AD9779 Noise Spectral Density vs. f Single-Tone Input at −6 dBFS –55 –60 –65 –3dBFS ...
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AD9776/AD9778/AD9779 REF –25.28dBm *ATTEN 4dB *AVG Log 10dB/ PAVG CENTER 143.88MHz *RES BW 30kHz VBW 300kHz SWEEP 162.2ms (601 pts) LOWER RMS RESULTS FREQ OFFSET REF BW dBc dBm CARRIER POWER 5.000MHz 3.840MHz –76.75 –89.23 –12.49dBm/ 10.00MHz ...
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OUT Figure 38. AD9778 IMD, 4× Interpolation 100 90 f DATA f = 160MSPS DATA 250MSPS DATA ...
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AD9776/AD9778/AD9779 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 2560 CODE Figure 44. AD9776 Typical INL 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0 512 1024 1536 2048 2560 CODE Figure 45. ...
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DAC –154 f = 400MSPS DAC –158 f = 800MSPS DAC –162 –166 –170 (MHz) OUT Figure 50. AD9776 Noise Spectral Density vs. f DAC with 500 ...
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AD9776/AD9778/AD9779 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure ...
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THEORY OF OPERATION The AD9776/AD9778/AD9779 combine many features that make them very attractive DACs for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single ...
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AD9776/AD9778/AD9779 For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the device based on the LSB-first bit (Register 0x00, Bit 6). Table 10. Byte Transfer Count N1 N0 Description 0 0 Transfer ...
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SPI REGISTER MAP Table 11. Register Name Address Bit 7 Comm 0x00 00 SDIO Bidirectional Digital 0x01 01 Filter Interpolation Factor<1:0> Control 0x02 02 Data Format Sync 0x03 03 Data Clock Delay Mode<1:0> Control 0x04 04 0x05 05 0x06 06 ...
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AD9776/AD9778/AD9779 Table 12. SPI Register Description Address Register Name Reg. No. Bits Comm Register Digital Control Register 01 7 ...
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Address Register Name Reg. No. Bits Sync Control Register 06 7 4:0 PLL Control 08 7 6:5 09 4:3 09 2:0 Misc Control 0A 7:5 0A ...
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AD9776/AD9778/AD9779 Address Register Name Reg. No. Bits Q DAC Control Register 0F 7 1:0 Aux DAC2 Control 11 7:0 Register 1:0 Interrupt Register ...
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INTERPOLATION FILTER ARCHITECTURE The AD9776/AD9778/AD9779 can provide up to 8× interpola- tion, or the interpolation filters can be entirely disabled important to note that the input signal should be backed off by approximately 0.01 dB from full scale ...
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AD9776/AD9778/AD9779 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 – (× Input Data Rate) OUT Figure 59. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB ...
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Input Data Rate) OUT Figure 65. Interpolation/Modulation Combination –10 –20 –30 –40 –50 –60 –70 –80 ...
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AD9776/AD9778/AD9779 Table 17. Interpolation Filter Modes, (Register 0x01, Bits<5:2>) Filter Interpolation Mode Factor <7:6> <5:2> Modulation 8 0x00 DC 8 0x01 DC shifted 8 0x02 F/8 8 0x03 F/8 shifted 8 0x04 F/4 8 0x05 F/4 shifted 8 0x06 3F/8 ...
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INTERPOLATION FILTER MINIMUM AND MAXIMUM BANDWIDTH SPECIFICATIONS The AD977x uses a novel interpolation filter architecture that allows DAC IF frequencies to be generated anywhere in the spectrum. Figure 68 shows the traditional choice of DAC IF output bandwidth placement. Note ...
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AD9776/AD9778/AD9779 0.1μF LVDS_P_IN 50Ω 50Ω LVDS_N_IN 0.1μF Figure 71. LVDS REFCLK Drive Circuit If a clean sine clock is available, it can be transformer-coupled to REFCLK, as shown in Figure 71. Use of a CMOS or TTL clock is also ...
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Table 18. VCO Frequency Range vs. PLL Band Select Value Typical PLL Lock Ranges PLL Band Select VCO Frequency Range in MHz Typ at 25° LOW HIGH 111111 (63) Auto mode 111110 (62) 2056 2170 111101 (61) 2002 ...
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AD9776/AD9778/AD9779 (Register 0x09, Bits<2:0>) should be set to 111. The PLL control voltage (Register 0x0A, Bits<7:5>) is read back and is propor- tional to the dc voltage at the internal loop filter output. With the PLL bias settings given in ...
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V to 1.6 V. When sinking current, the output compliance voltage is 0 1.6 V. The auxiliary DACs can be used for local oscillator (LO) cancella- tion when the DAC output is followed by a ...
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AD9776/AD9778/AD9779 0.075 ALL INTERPOLATION MODES 0.050 0.025 100 125 150 f (MSPS) DATA Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation Modes and Zero Stuffing 1.0 8× INTERPOLATION, ALL MODULATION ...
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POWER-DOWN AND SLEEP MODES The AD977x has a variety of power-down modes, so that the digital engine, main TxDACs, or auxiliary DACs can be powered down individually or together. Via the SPI port, the main TxDACs can be placed in ...
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AD9776/AD9778/AD9779 REFERENCE CLOCK IN CLOCK OUT Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1× SYNC_IN REFERENCE CLOCK IN DATA CLOCK OUT INPUT DATA Figure 93. Timing Specifications, PLL Enabled or Disabled, Interpolation = 2× SYNC_IN REFERENCE CLOCK ...
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Specifications are given in Table 19 for the drift of input data set up and hold time vs. temperature, as well as the data keep out window (KOW). Note that although these specifications do drift, the length of the keep ...
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AD9776/AD9778/AD9779 Using Data Delay to Meet Timing Requirements To meet strict timing requirements at input data rates 250 MSPS, the AD977x has a fine timing feature. Fine timing adjustments are made by programming values into the data ...
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In addition to this divisor function, DATACLK can be divided additional factor of 4, according to the state of the DATACLK divide register (Register 0x03, Bits<5:4>). For more details, see Table 22). Table 22. Extra DATACLK ...
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AD9776/AD9778/AD9779 EVALUATION BOARD OPERATION The AD977x evaluation board is designed to optimize the DAC performance and the speed of the digital interface, yet remains user friendly. To operate the board, the user needs a power source, a clock source, and ...
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The default settings for the evaluation board allow the user to view the differential outputs through a transformer that converts the DAC output signal to a single-ended signal. On the evaluation board, these transformers are designated T1A, T2A, T3A, and ...
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AD9776/AD9778/AD9779 MODIFYING THE EVALUATION BOARD TO USE THE AD8349 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices quadrature modulator. The AD977x and AD8349 provide an easy-to-interface DAC/modulator combination that can be easily evaluated on the evaluation board. To ...
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EVALUATION BOARD SCHEMATICS Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface AD9776/AD9778/AD9779 Rev Page ...
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AD9776/AD9778/AD9779 T2B T1B ADTL1-12 ADTL1-12 T2A T1A TC1-1T TC1-1T C62 C33 0.1µF 1nF JP4 D1P ...
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R15 20Ω D1N C64 17.2pF R17 150Ω AUX1_N R4 R19 150Ω 300Ω AUX1_P R12 150Ω C63 17.2pF D1P R16 20Ω VDDM C41 10µF 10V DGND2 R24 20Ω D2N C44 17.2pF R25 150Ω AUX2_N R2 R27 150Ω 300Ω AUX2_P R3 150Ω ...
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AD9776/AD9778/AD9779 A10 B10 A11 B11 A15 B15 A16 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 B21 A22 ...
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Figure 110. Evaluation Board, Rev. D, Top Silk Screen Figure 111. Evaluation Board, Rev. D, Top Layer Rev Page AD9776/AD9778/AD9779 ...
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AD9776/AD9778/AD9779 Figure 112. Evaluation Board, Rev. D, Layer 2 Figure 113. Evaluation Board, Rev. D, Layer 3 Rev Page ...
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Figure 114. Evaluation Board, Rev. D, Bottom Layer Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen Rev Page AD9776/AD9778/AD9779 ...
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... AD9778BSVZ −40°C to +85°C AD9778BSVZRL 1 −40°C to +85°C 1 AD9779BSVZ −40°C to +85°C 1 AD9779BSVZRL −40°C to +85°C AD9776-EB AD9778-EB 1 AD9779-EBZ RoHS Compliant Part. ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...