AD9779BSVZ Analog Devices Inc, AD9779BSVZ Datasheet - Page 39

• Manufacturer Part Number: AD9779BSVZ
• Description: IC DAC 16BIT DUAL 1GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779BSVZ

• Data Interface: Serial
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 160
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

voltage is 0 V to 1.6 V. When sinking current, the output
compliance voltage is 0.8 V to 1.6 V.
The auxiliary DACs can be used for local oscillator (LO) cancella-
tion when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 79
and Figure 80. Often, the input common-mode voltage for the
modulator is much higher than the output compliance range of
the DAC, so that ac coupling or a dc level shift is necessary. If the
required common-mode input voltage on the quadrature
modulator matches that of the DAC, then the dc blocking
capacitors in Figure 79 can be removed. A low-pass or band-pass
passive filter is recommended when spurious signals from the
DAC (distortion and DAC images) at the quadrature modulator
inputs can affect the system performance. Placing the filter at the
location shown in Figure 79 and Figure 80 allows easy design of
the filter, as the source and load impedances can easily be
designed close to 50 Ω.
POWER DISSIPATION
Figure 81 to Figure 89 show the power dissipation of the 1.8 V
and 3.3 V digital and clock supplies in single DAC and dual
DAC modes. In addition to this, the power dissipation/current
25Ω TO 50Ω
AD9779
I DAC
Figure 80. Typical Use of Auxiliary DACs DC Coupling to Quadrature
I OR Q DAC
Figure 79. Typical Use of Auxiliary DACs AC Coupling to
AD9779
25Ω TO 50Ω
0.1μF
0.1μF
OPTIONAL
FILTERING
PASSIVE
25Ω TO 50Ω
AD9779
Q DAC
Modulator with DC Shift
Quadrature Modulator
MODULATOR V+
QUADRATURE
DAC1 OR 2
FILTERING
OPTIONAL
PASSIVE
AD9779
AUX
0.1μF
0.1μF
MODULATOR V+
AD9779
QUADRATURE
DAC1
AUX
QUAD MOD
I INPUTS
FILTERING
OPTIONAL
PASSIVE
25Ω TO 50Ω
MODULATOR V+
QUAD MOD
I OR Q INPUTS
QUADRATURE
AD9779
DAC2
AUX
QUAD MOD
Q INPUTS
Rev. A | Page 39 of 56
of the 3.3 V supply (mode and speed independent) in single
DAC mode is 102 mW/31 mA. In dual DAC mode, this is
182 mW/55 mA. Furthermore, when the PLL is enabled, it adds
90 mW/50 mA to the 1.8 V clock supply regardless of the mode
of the AD9779.
Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,
Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,
0.08
0.06
0.04
0.02
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.4
0.3
0.2
0.1
Includes Modulation Modes, Does Not Include Zero Stuffing
Figure 81. Total Power Dissipation, I Data Only, Real Mode
0
0
0
0
0
0
8 × INTERPOLATION
25
25
25
8 × INTERPOLATION,
ZERO STUFFING
8 × INTERPOLATION
50
50
50
Does Not Include Zero Stuffing
75
75
75
AD9776/AD9778/AD9779
100
100
100
f
f
f
DATA
DATA
DATA
8 × INTERPOLATION
125
125
125
(MSPS)
(MSPS)
(MSPS)
4 × INTERPOLATION,
4 × INTERPOLATION
4 × INTERPOLATION
ZERO STUFFING
150
150
150
2 × INTERPOLATION
2 × INTERPOLATION
1 × INTERPOLATION
1 × INTERPOLATION
175
175
175
2 × INTERPOLATION,
1 × INTERPOLATION,
4 × INTERPOLATION
2 × INTERPOLATION
1 × INTERPOLATION
ZERO STUFFING
ZERO STUFFING
200
200
200
225
225
225
250
250
250