LM4856LQX/NOPB National Semiconductor, LM4856LQX/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM4856LQX/NOPB
• Manufacturer: National Semiconductor

Specifications of LM4856LQX/NOPB

• Operational Class: Class-AB
• Audio Amplifier Function: Headphone/Speaker
• Total Harmonic Distortion: 0.5@8Ohm@400mW%
• Single Supply Voltage (typ): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Supply Current (max): 12@5VmA
• Power Supply Requirement: Single
• Rail/rail I/o Type: No
• Power Supply Rejection Ratio: 68dB
• Single Supply Voltage (min): 2.6V
• Single Supply Voltage (max): 5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: LLP
• Lead Free Status / Rohs Status: Compliant

www.national.com
Application Information
I
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADR: This is the address select input pin.
I
The LM4856 uses a serial bus, which conforms to the I
protocol, to control the chip’s functions with two wires: clock
and data. The clock line is uni-directional. The data line is
bi-directional (open-collector) with a pullup resistor (typically
10kΩ).The maximum clock frequency specified by the I
standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4856.
The I
ADR pin. The LM4856’s two possible I
of the form 110110X
logic low; and X
is used to address a number of chips in a system and the
LM4856’s chip address can be changed to avoid address
conflicts.
The timing diagram for the I
is latched in on the stable high level of the clock and the data
line should be held high when not in use. The timing diagram
is broken up into six major sections:
2
2
C PIN DESCRIPTION
C INTERFACE
2
C address for the LM4856 is determined using the
1
= 1, if ADR is logic high. If the I
1
0 (binary), where the X
2
C is shown in Figure 2. The data
2
C chip addresses are
1
= 0, if ADR is
FIGURE 3. I
2
C interface
FIGURE 2. I
2
2
C
C
2
C Timing Diagram
2
14
C Bus Format
The “start” signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I
dress against their own chip address.
The 8-bit chip address is sent next, most significant bit first.
Each address bit must be stable while the clock level is high.
After the last bit of the address is sent, the master checks for
the LM4856’s acknowledge. The master releases the data
line high (through a pullup resistor). Then the master sends
a clock pulse. If the LM4856 has received the address
correctly, then it holds the data line low during the clock
pulse. If the data line is not low, then the master should send
a “stop” signal (discussed later) and abort the transfer.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must generate another
acknowledge to see if the LM4856 received the data.
If the master has more data bytes to send to the LM4856,
then the master can repeat the previous two steps until all
data bytes have been sent.
The “stop” signal ends the transfer. To signal “stop”, the data
signal goes high while the clock signal is high.
2
C bus to check the incoming ad-
200607F4
200607F5