SCAN92LV090VEH National Semiconductor, SCAN92LV090VEH Datasheet

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SCAN92LV090VEH

Manufacturer Part Number
SCAN92LV090VEH
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of SCAN92LV090VEH

Number Of Elements
2
Number Of Receivers
2
Number Of Drivers
2
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Differential Output Voltage
460mV
Propagation Delay Time
3.9ns
Power Dissipation
1.74W
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant

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Manufacturer
Quantity
Price
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Part Number:
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Texas Instruments
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Part Number:
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© 2007 National Semiconductor Corporation
SCAN92LV090
9 Channel Bus LVDS Transceiver w/ Boundary SCAN
General Description
The SCAN92LV090A is one in a series of Bus LVDS
transceivers designed specifically for the high speed, low
power proprietary backplane or cable interfaces. The device
operates from a single 3.3V power supply and includes nine
differential line drivers and nine receivers. To minimize bus
loading, the driver outputs and receiver inputs are internally
connected. The separate I/O of the logic side allows for loop
back support. The device also features a flow through pin out
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differ-
ential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V com-
mon mode range and translates the differential Bus LVDS to
standard (TTL/CMOS) levels.
This device is compliant with IEEE 1149.1 Standard Test Ac-
cess Port and Boundary Scan Architecture with the incorpo-
ration of the defined boundary-scan test logic and test access
Simplified Functional Diagram
Connection Diagrams
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
101242
port consisting of Test Data Input (TDI), Test Data Out (TDO),
Test Mode Select (TMS), Test Clock (TCK), and the optional
Test Reset (TRST).
Features
IEEE 1149.1 (JTAG) Compliant
Bus LVDS Signaling
Low power CMOS design
High Signaling Rate Capability (above 100 Mbps)
0.1V to 2.3V Common Mode Range for V
±100 mV Receiver Sensitivity
Supports open and terminated failsafe on port pins
3.3V operation
Glitch free power up/down (Driver & Receiver disabled)
Light Bus Loading (5 pF typical) per Bus LVDS load
Designed for Double Termination Applications
Balanced Output Impedance
Product offered in 64 pin LQFP package and BGA
package
High impedance Bus pins on power off (V
10124201
December 2006
ID
CC
www.national.com
= 200mV
= 0V)

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SCAN92LV090VEH Summary of contents

Page 1

... Simplified Functional Diagram Connection Diagrams TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). ...

Page 2

... Top View Order Number SCAN92LV090VEH See NS Package Number VEH064DB Top View Order Number SCAN92LV090SLC See NS Package Number SLC64A 2 10124202 10124216 ...

Page 3

Pinout Description Pin Name TQFP Pin # DO+/RI+ 27, 31, 35, 37, 41, 45, A7, B8, C6, D5, D8, E6, 47, 51, 55 DO−/RI− 26, 30, 34, 36, 40, 44, B5, B6, C7, D6, E5, E8, 46, 50 ...

Page 4

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Enable Input Voltage (DE, RE) Driver Input Voltage ( Receiver Output Voltage (R ) OUT Bus Pin Voltage (DO/RI±) ESD (HBM 1.5 kΩ, 100 pF) ...

Page 5

Symbol Parameter I Input High Current IH I Input Low Current ILR I Input Low Current IL I Power Supply Current CCD Drivers Enabled, Receivers Disabled I Power Supply Current CCR Drivers Disabled, Receivers Enabled I Power Supply Current, CCZ ...

Page 6

Symbol Parameter t Differential Prop. Delay High to Low (Note 8) PHLD t Differential Prop Delay Low to High (Note 8) PLHD t Differential Skew |t –t SDK1 PHLD t Chip to Chip Skew (Note 12) SDK2 t Channel to ...

Page 7

Applications Information General application guidelines and hints may be found in the following application notes: AN-808, AN-1108, AN-977, AN-971, and AN-903. There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices ...

Page 8

FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms www.national.com FIGURE 4. Driver TRI-STATE Delay Test Circuit FIGURE 5. Driver TRI-STATE Delay Waveforms 8 10124205 10124206 10124207 ...

Page 9

FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms FIGURE 8. Receiver TRI-STATE Delay Test Circuit FIGURE 9. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations 10124208 10124214 10124215 10124211 ...

Page 10

Bi-Directional Half-Duplex Point-to-Point Applications Multi-Point Bus Applications 10 10124212 10124213 ...

Page 11

Description of Boundary-Scan Circuitry The SCAN92LV090 features two unique Scan test modes, each which requires a unique BSDL model depending on the level of test access and fault coverage goals. In the first mode (Mode0), only the TTL Inputs and ...

Page 12

... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 64-Lead Molded LQFP Package Order Number SCAN92LV090VEH NS Package Number VEH064DB 64-Lead Ball Grid Array Package Order Number SCAN92LV090SLC NS Package Number SLC64A 12 ...

Page 13

Notes 13 www.national.com ...

Page 14

... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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