CY7C4282V-15ASC Cypress Semiconductor Corp, CY7C4282V-15ASC Datasheet
CY7C4282V-15ASC
Specifications of CY7C4282V-15ASC
Related parts for CY7C4282V-15ASC
CY7C4282V-15ASC Summary of contents
Page 1
... Functional Description The CY7C4282V/92V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All devices are nine bits wide. The CY7C4282V/92V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communica- tions buffering ...
Page 2
... The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is LOW, RCLK reads data out of the programmable flag-offset register. CY7C4282V CY7C4292V Q 5 ...
Page 3
... CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Architecture The CY7C4282V/92V consists of an array of 64K to 128K words of 9 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF). ...
Page 4
... LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO (MSB) is greater than or equal to CY7C4282V (64K – m) and Default Value = 000h CY7C4292V (128K – m). PAF is set HIGH by the LOW-to- HIGH transition of WCLK when the number of available 0 memory locations is greater than m ...
Page 5
... A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demon- strates a 18-bit word width by using two CY7C4282V/92V. Any word width can CY7C4282V/92V ...
Page 6
... Depth Expansion Configuration The CY7C4282V/92V can easily be adapted to applications requiring more than 64K/128K words of buffering. Figure 3 shows Depth Expansion using three CY7C4282V/92Vs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. ...
Page 7
... Com’l 25 Ind Com’l 6 Ind Test Conditions MHz 3.3V CC [10, 11] 3.0V R2=510 GND 3 ns 2.0V CY7C4282V CY7C4292V +0.5V CC [6] Ambient Temperature +70 C 3.3V 300 +85 C 3.3V 300 mV 7C4282V/92V 7C4282V/92V -15 -25 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0 ...
Page 8
... Pulse widths less than minimum values are not allowed. 13. Values guaranteed by design, not currently tested. Document #: 38-06014 Rev. *B [10, 11] (continued) ALL INPUT PULSES 3.0V 90% 10% GND 3 ns 7C4282V/92V 7C4282V/92V -10 Min. Max. Min. 100 4.5 6 4 [13 [13 CY7C4282V CY7C4292V 90% 10 7C4282V/92V -15 -25 Max. Min. Max. Unit 66.7 40 MHz ...
Page 9
... CLK t CLKL NO OPERATION t REF VALID DATA t OE [15] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4282V CY7C4292V NO OPERATION t WFF REF t OHZ Page [+] Feedback ...
Page 10
... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06014 Rev RSS RSR t RSF t RSF t RSF [19] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW1 CY7C4282V CY7C4292V [18] OE=1 OE [20 (maximum) = either 2 FRL CLK SKEW1 CLK SKEW1 Page [+] Feedback ...
Page 11
... DATA IN OUTPUT REGISTER 0 8 Document #: 38-06014 Rev DATA WRITE 2 t ENS REF REF SKEW2 t A [14 SKEW1 DATA WRITE t WFF t ENS DATA READ CY7C4282V CY7C4292V t ENH [19] t FRL t REF DATA READ NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ Page [+] Feedback ...
Page 12
... If a read is performed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW 24 write is performed on this rising edge of the write clock, there will be Full 25. 64K m words for CY7C4282V, 128K m words for CY4292V. 26 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and ...
Page 13
... Document #: 38-06014 Rev CLKL t ENH t DH PAE OFFSET PAF OFFSET LSB MSB t CLKL t ENH t A UNKNOWN PAE OFFSET LSB t PRT to update these flags. RTR CY7C4282V CY7C4292V PAF OFFSET LSB MSB PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB t RTR . RTR Page [+] Feedback ...
Page 14
... Ordering Information 64K x 9 Low Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4282V-10ASC 15 CY7C4282V-15ASC CY7C4282V-15ASI 128K x 9 Low Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4292V-10ASC 15 CY7C4292V-15ASC CY7C4292V-15ASI Package Diagram 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64 All product and company names mentioned in this document are the trademarks of their respective holders. ...
Page 15
... Document History Page Document Title: CY7C4282V/CY7C4292V 64K/128K x 9 Low-Voltage Deep Sync FIFOs with Retransmit and Depth Expansion Document Number: 38-06014 REV. ECN NO. Issue Date ** 106475 09/15/01 *A 122266 12/26/02 *B 127859 08/25/03 Document #: 38-06014 Rev. *B Orig. of Change Description of Change SZV Change from Spec number: 38-00657 to 38-06014 ...