CY7C4282V-15ASC Cypress Semiconductor Corp, CY7C4282V-15ASC Datasheet - Page 5

• Manufacturer Part Number: CY7C4282V-15ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-15ASC

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 64Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 25mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06014 Rev. *B
Table 2. Status Flags
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read
since the last RS cycle. A HIGH pulse on RT resets the internal
read pointer to the first physical location of the FIFO. WCLK
and RCLK may be free running but must be disabled during
and t
after retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Notes:
0
1 to n
(n + 1) to (65536
(65536
65536
2.
3.
FULL FLAG (FF)
n = Empty Offset (n = 7 default value).
m = Full Offset (m = 7 default value).
RTR
DATA IN (D)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
[2]
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
after the retransmit pulse. With every valid read cycle
m)
[3]
to 65535
CY7C4282V
Figure 2. Block Diagram of 64K × 9/128K × 9 Low-Voltage Deep Sync FIFO Memory
LOAD (LD)
(m + 1))
18
9
Number of Words in FIFO
FIRST LOAD (FL)
EXPANSION IN (XI)
FF
RESET (RS)
7C4282V
7C4292V
Used in a Width-Expansion Configuration
0
1 to n
(n + 1) to (131072
(131072
131072
[2]
EF
m)
9
[3]
CY7C4292V
to 131071
(m + 1))
9
Width-Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input control signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C4282V/92V. Any
word
CY7C4282V/92V.
When the CY7C4282V/92V is in a Width Expansion Configu-
ration, the Read Enable (REN) control input can be grounded
(see Figure 2). In this configuration, the Load (LD) pin is set to
LOW at Reset so that the pin operates as a control to load and
read the programmable flag offsets.
FIRST LOAD (FL)
EXPANSION IN (XI)
FF
width
RESET (RS)
7C4282V
7C4292V
can
be
EF
FF
H
H
H
H
L
attained
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
9
PAF
H
H
H
DATA OUT (Q)
L
L
by
EMPTY FLAG (EF)
CY7C4282V
CY7C4292V
adding
PAE
H
H
H
L
L
Page 5 of 15
additional
18
EF
H
H
H
H
L
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