MT47H128M16HG-37E:A TR Micron Technology Inc, MT47H128M16HG-37E:A TR Datasheet - Page 114

• Manufacturer Part Number: MT47H128M16HG-37E:A TR
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M16HG-37E:A TR

• Organization: 128Mx16
• Address Bus: 17b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 195mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 67: Data Input Timing
PRECHARGE
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Notes:
DQS#
Precharge can be initiated by either a manual PRECHARGE command or by an autopre-
charge in conjunction with either a READ or WRITE command. Precharge will deacti-
vate the open row in a particular bank or the open row in all banks. The PRECHARGE
operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all
banks are to be precharged. In the case where only one bank is to be precharged, bank
address inputs determine the bank to be precharged. When all banks are to be pre-
charged, the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to
any READ or WRITE commands being issued to that bank. When a single-bank PRE-
CHARGE command is issued,
mand is issued,
DQS
CK#
DM
DQ
CK
1.
2.
3. Subsequent rising DQS signals must align to the clock within
4. WRITE command issued at T0.
5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
t
t
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
T0
WL - t DQSS (NOM)
t
RPA timing applies, regardless of the number of banks opened.
T1
T1n
t WPRE
114
t
T2
DI
RP timing applies. When the PRECHARGE (ALL) com-
t DSH 1
T2n
t DQSL
t DSS 2
t
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Transitioning Data
T3
3
t DQSH
t DSH 1
T3n
2Gb: x4, x8, x16 DDR2 SDRAM
t WPST
t DSS 2
T4
Don’t Care
© 2006 Micron Technology, Inc. All rights reserved.
t
DQSS.
PRECHARGE