MT48LC2M32B2P-5:G Micron Technology Inc, MT48LC2M32B2P-5:G Datasheet

IC SDRAM 64MBIT 200MHZ 86TSOP

MT48LC2M32B2P-5:G

Manufacturer Part Number
MT48LC2M32B2P-5:G
Description
IC SDRAM 64MBIT 200MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC2M32B2P-5:G

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOP
Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
4.5ns
Maximum Clock Rate
200MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
280mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Package
86TSOP-II
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
4.5 ns
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!"
Synchronous DRAM
MT48LC2M32B2 – 512K x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site
Features
• PC100 functionality
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode (not available on AT devices)
• Refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Notes: 1. Off-center parting line.
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_1.fm - Rev. J 12/08 EN
Options
• Configuration
• Plastic package – OCPL
• Timing (cycle time)
• Die revision
• Operating temperature range
edge of system clock
changed every clock cycle
and auto refresh modes
– 64ms, 4,096-cycle refresh (15.6µs/row)
– 16ms, 4,096-cycle refresh (3.9µs/row)
– 2 Meg x 32 (512K x 32 x 4 banks)
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm) Pb-free
– 5ns (200 MHz)
– 5.5ns (183 MHz)
– 6ns (166 MHz)
– 7ns (143 MHz)
– Commercial (0° to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
(commercial, industrial)
(automotive)
2. Available on -6 and -7.
3. Contact Micron for product availability.
Products and specifications discussed herein are subject to change by Micron without notice.
1
Marking
2M32B2
None
AT
-55
IT
TG
B5
:G
-5
-6
-7
P
2
3
1
Table 1:
Table 2:
Table 3:
Notes: 1. FBGA Device Decode: http://
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
MT48LC2M32B2TG
MT48LC2M32B2P
MT48LC2M32B2B5
Speed
Grade
-55
-5
-6
-7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Part Number
www.micron.com/support/FBGA/FBGA.asp
Frequency
200 MHz
183 MHz
166 MHz
143 MHz
Address Table
Key Timing Parameters
CL = CAS (READ) latency
64Mb (x32) SDRAM Part Number
Clock
MT48LC2M32B2P-7:G
Part Number Example:
1
Access
CL = 3
Time
4.5ns
5.5ns
5.5ns
5ns
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
512K x 32 x 4 banks
Architecture
4 (BA0, BA1)
2K (A0–A10)
2 Meg x 32
256 (A0–A7)
Setup
2 Meg x 32
2 Meg x 32
2 Meg x 32
Time
1.5ns
1.5ns
1.5ns
2ns
4K
Features
Hold
Time
1ns
1ns
1ns
1ns

Related parts for MT48LC2M32B2P-5:G

MT48LC2M32B2P-5:G Summary of contents

Page 1

... SDRAM Part Number 2M32B2 Part Number TG MT48LC2M32B2TG P MT48LC2M32B2P B5 MT48LC2M32B2B5 -5 Notes: 1. FBGA Device Decode: http:// -55 www.micron.com/support/FBGA/FBGA.asp - MT48LC2M32B2P-7:G None Micron Technology, Inc., reserves the right to change products or specifications without notice. 1 64Mb: x32 SDRAM Features 2 Meg x 32 512K banks 4K 2K (A0–A10) 4 (BA0, BA1) 256 (A0–A7) ...

Page 2

... Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 64Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. ...

Page 3

Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of Figures Figure 1: 2 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

... ADDRESS 13 BA0, BA1 REGISTER PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN BANK 0 11 BANK 0 ROW- 11 ROW- ADDRESS ADDRESS MUX MEMORY 2048 LATCH & (2,048 x 256 x 32) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC ...

Page 7

Pin/Ball Assignments and Descriptions Figure 2: 86-Pin TSOP (Top View DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM0 WE# CAS# RAS# CS# ...

Page 8

Figure 3: 90-Ball VFBGA (Top View, Ball Down PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN Pin/Ball Assignments and Descriptions ...

Page 9

... Address inputs: A0–A10 are sampled during the ACTIVE command (row-address A0–A10) and READ/WRITE command (column-address A0–A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW) ...

Page 10

Table 4: Pin/Ball Descriptions (continued) 86-Pin TSOP 90-Ball VFBGA Numbers Numbers 3, 9, 35, 41, 49, B2, B7, C9, D9, 55, 75, 81 E1, L1, M9, N9, P2 12, 32, 38, B8, B3, C1, D1, 46, 52, 78, ...

Page 11

When in the idle state, at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program- ming. Because the mode register will power unknown ...

Page 12

Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CL, an operating mode and a write burst ...

Page 13

Figure 4: Mode Register Definition A10, BA0, and BA1 = “0” to ensure compatibility with future devices. Write Burst Mode M9 0 Programmed Burst Length 1 Single Location Access M8 M7 M6– Defined – – – Burst Type ...

Page 14

Table 5: Burst Definition Burst Length Full page (256) Notes: 1. For A1–A7 select the block-of-two burst; A0 selects the starting column within the block. 2. For A2–A7 select the block-of-four burst; A0–A1 select ...

Page 15

Figure 5: CAS Latency COMMAND COMMAND COMMAND Table 6: CAS Latency Speed -5 - PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP OUT ...

Page 16

Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; other combina- tions of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read ...

Page 17

... DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. ...

Page 18

PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( whether one or all ...

Page 19

REFRESH command except CKE is disabled (LOW). When the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. After self refresh mode is engaged, the SDRAM ...

Page 20

Figure 6: Activating a Specific Row in a Specific Bank CLK CKE CS# RAS# CAS# WE# A0–A10 BA0, BA1 Figure 7: Example: Meeting CLK COMMAND t Notes: 1. RCD (MIN) = 20ns RCD (MIN) x READs READ bursts ...

Page 21

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from ...

Page 22

Figure 9: CAS Latency COMMAND COMMAND COMMAND PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP OUT CLK READ NOP t LZ ...

Page 23

Figure 10: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP NOP BANK, ...

Page 24

Figure 11: Random READ Accesses COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a ...

Page 25

Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE ...

Page 26

Figure 13: READ-to-WRITE With Extra Clock Cycle DQM COMMAND ADDRESS Note used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. A fixed-length READ burst may ...

Page 27

Figure 14: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP NOP BANK a, COL OUT OUT ...

Page 28

Figure 15: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/ CLK READ NOP NOP BANK, COL OUT OUT DQ ...

Page 29

WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge ...

Page 30

Figure 17: WRITE Burst COMMAND ADDRESS Figure 18: WRITE-to-WRITE COMMAND ADDRESS TRANSITIONING DATA Note: DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data ...

Page 31

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvan- tage ...

Page 32

Figure 21: WRITE-to-PRECHARGE CLK ( DQM COMMAND ADDRESS CLK (when DQM COMMAND ADDRESS Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length ...

Page 33

Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress (see Figure 24 on page 34). If power-down occurs when all banks are idle, this mode is referred to ...

Page 34

Figure 23: PRECHARGE Command CLK CKE CS# RAS# CAS# WE# A0–A9 A10 BA0, 1 Figure 24: Power-Down CLK CKE COMMAND All banks idle Enter power-down mode. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress ...

Page 35

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Burst Read/Single Write The burst read/single write mode is entered by programming the write burst mode bit ...

Page 36

Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. ...

Page 37

Figure 28: READ with Auto Precharge Interrupted by a WRITE CLK COMMAND Page BANK n Active Internal States BANK m ADDRESS 1 DQM DQ Notes: 1. DQM is HIGH prevent D Figure 29: WRITE with Auto Precharge ...

Page 38

Figure 30: WRITE with Auto Precharge Interrupted by a WRITE CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Note: DQM is LOW. Table 8: Truth Table 2 – CKE Notes: 1–4 apply to entire table CKE CKE Current ...

Page 39

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n Notes 1–6 apply to entire table; notes appear below and on next page Current State CS# RAS# Any Idle ...

Page 40

The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 6. All states and sequences not ...

Page 41

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m Notes 1–6 apply to entire table; notes appear below and on next page Current State CS# RAS# Any Idle X X Row ...

Page 42

A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...

Page 43

Electrical Specifications Stresses greater than those listed in Table 11 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...

Page 44

Table 12: Temperature Limits Parameter Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figures 31 ...

Page 45

Figure 31: Example Temperature Test Point Location, 86-Pin TSOP (Top View) Test point Figure 32: Example Temperature Test Point Location, 90-Ball FBGA (Top View) Test point PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 64MSDRAMx32_2.fm - Rev. J 12/08 EN 22.22mm 11.11mm 8.00mm 4.00mm 13.00mm ...

Page 46

Table 14: DC Electrical Characteristics and Operating Conditions Notes apply to entire table; notes appear on pages 49 and 50; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All ...

Page 47

Table 18: Electrical Characteristics and Recommended AC Operating Conditions Notes apply to entire table; notes appear on pages 49 and 50 Characteristics Parameter Access time from CLK (positive edge) CL ...

Page 48

Table 19: AC Functional Characteristics Notes apply to entire table; notes appear on pages 49 and 50 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable ...

Page 49

Notes 1. All voltages referenced This parameter is sampled. V biased at 1.4V. AC can range from 0pF to 6pF with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address ...

Page 50

The clock frequency must remain constant during access or precharge states (READ, WRITE, including data rate. 24. Auto precharge mode only. 25. JEDEC and PC100 specify three clocks 7ns for -7, 6ns for -6, 5.5ns ...

Page 51

Timing Diagrams Figure 33: Initialize and Load Mode Register CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ...

Page 52

Figure 34: Power-Down Mode T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0-3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all active ...

Page 53

Figure 35: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM0– A0–A9 COLUMN ...

Page 54

Figure 36: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0–3 A0–A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active ...

Page 55

Figure 37: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM0–3 A0–A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks ...

Page 56

Figure 38: Single READ T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0-A9 ROW ROW A10 BA0, BA1 BANK ...

Page 57

Figure 39: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 ROW A0- ROW A10 DISABLE ...

Page 58

Figure 40: READ – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9 ROW ENABLE AUTO PRECHARGE ROW ...

Page 59

Figure 41: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 ROW A0- ENABLE AUTO PRECHARGE ROW A10 ...

Page 60

Figure 42: READ – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ t CMS DQM 0 A0-A9 COLUMN m ...

Page 61

Figure 43: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 ...

Page 62

Figure 44: Single WRITE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0-A9 ROW ROW A10 ...

Page 63

Figure 45: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9 ROW ROW A10 DISABLE AUTO ...

Page 64

Figure 46: WRITE – with Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP WRITE t CMS DQM 0 A0-A9 COLUMN m 3 ...

Page 65

Figure 47: Alternating Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 3 A0-A9 ROW t ...

Page 66

Figure 48: WRITE – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 ROW A0- ROW A10 t ...

Page 67

Figure 49: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM 0 A0-A9 ROW ROW A10 BA0, ...

Page 68

Package Dimensions Figure 50: 86-Pin Plastic TSOP II (400 mil) 22.22 ±0.08 0.50 TYP 0. 0.75 PIN # 1.00 PLATED LEAD FINISH: TG (90% Sn, 10% Pb (100% Sn) 0.01 ±0.005 THICK PER ...

Page 69

Figure 51: 90-Ball VFBGA (8mm x 13mm) 0.65 ±0.05 SEATING PLANE C 0.10 C 90X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø0.42 BALL A9 11.20 ±0.10 5.60 ±0.05 3.20 ±0.05 Notes: ...

Related keywords