SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet

SL72P8M64M8M-A05AYU

Manufacturer Part Number

SL72P8M64M8M-A05AYU

Description

Manufacturer

STEC

Datasheet

1.SL72P8M64M8M-A05AYU.pdf (19 pages)

Specifications of SL72P8M64M8M-A05AYU

Main Category

DRAM Module

Sub-category

DDR2 SDRAM

Module Type

240RDIMM

Device Core Size

72b

Organization

64Mx72

Total Density

512MByte

Chip Density

512Mb

Access Time (max)

600ps

Maximum Clock Rate

400MHz

Operating Supply Voltage (typ)

1.8V

Operating Current

1.17A

Number Of Elements

Operating Supply Voltage (max)

1.9V

Operating Supply Voltage (min)

1.7V

Operating Temp Range

0C to 85C

Operating Temperature Classification

Commercial

Pin Count

240

Mounting

Socket

Lead Free Status / Rohs Status

Compliant

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64M X 72 Bit (512MB) 240-Pin DDR2 Registered RDIMM ECC (PC2-3200) 1 Rank x 8; RoHS Compliant ,Lead Free

GENERAL DESCRIPTION

The SL72P8M64M8M-A05AY(W)U is a 64M x 72 bit (512MB)

240-pin Double Data Rate 2 (DDR2) Registered Dual In-line

Memory Module (RDIMM) with data ECC support and optional

address/command parity support.

The module consists of nine CMOS 16M x 8 bit x 4 bank DDR2

SDRAMs in lead-free BGA packages mounted in 1 rank on a

240-pin glass epoxy substrate. The user has the option of

choosing industrial temperature rated SDRAM components.

A serial EEPROM using the two pin I

mounted to provide for the Serial Presence Detects (SPD).

Decoupling capacitors are mounted across the power supply.

FEATURES

ORDERING INFORMATION

Part Number

SL72P8M64M8M-A05AY(W)U

Notes:

• PC2-3200 Compliant

• 240-Pin RDIMM form factor

• Average periodic refresh interval (tREFI)

• VDD=VDDQ=1.8V + 0.1V

• VDDSPD=1.7V to 3.6V

• DDR2 architecture: Two data accesses per clock cycle,

• Commands entered on each rising CK edge; DQS-

1. Part numbers without the “W” select the Commercial Operating

2. Part Numbers with the “W” select the Industrial Operating Temperature

(DDR2-400 or faster bin operated at 200MHz,

5ns@CL-t

JEDEC standard 1.8V I/O (SSTL_18 compatible)

differential clock inputs (CK, /CK), bi-directional

differential data strobe (DQS, /DQS), Off-Chip Driver

(OCD) Impedance Adjustment, On Die Termination

(ODT), On Chip Delay Locked Loop (DLL); four-bit

prefetch architecture

edge aligned with data for READs and center-aligned

with data for WRITES; DLL to align DQ and DQS

transitions with CK

- 7.8125μs max for 0°C<Tcase<85°C

- 3.9μs max for 85°C<Tcase<95°C

Temperature range.

range. Inquire for availability.

(64ms / 8196 cycles)

(32ms / 8,196 cycles)

RCD

-t

: 3-3-3)

CL-tRCD-tRP

3-3-3

C protocol is also

DDR2-400 or faster

Chip Speed

Document Part Number 61000-03657-105 November 2007 Page 1

Damping resistors are added in series for DQ, DQS, and DM

signals. A PLL supplies clocks to the DDR2 SDRAMs from

one clock input.

All control and address signals are re-driven through registers

to the DDR2 SDRAM devices. The control/address input

signals are latched in the register on one rising clock edge

and sent to the SDRAM devices on the following rising clock

edge (data access is delayed by one clock).

The module has gold edge connections and is intended for

mounting into 240-pin RDIMM edge connector sockets keyed

for 1.8V.

SL72P8M64M8M-A05AY(W)U

• Four internal component banks for concurrent

• Concurrent Auto Precharge option is supported

• Data Mask (DM) for masking write data

• Programmable Burst lengths: 4, 8

• Programmable /CAS Latency (CL): 3, 4, 5

• Posted /CAS Additive Latency (AL): 0, 1, 2, 3, and 4

• WRITE latency = READ latency-1 tCK

• READ burst interrupt supported by another READ;

• Adjustable data-output drive strength

• Serial Presence Detect (SPD) with EEPROM

• Optional address/command parity support

• ECC, 1-bit error detection and correction

• Gold Edge contacts

• RoHS Compliant, lead free

• Commercial Operating Temperature

operation

WRITE burst interrupt supported by another WRITE

(Inquire for Industrial Operating Temperature

availability)

Module Speed

PC2-3200

Related parts for SL72P8M64M8M-A05AYU

SL72P8M64M8M-A05AYU Summary of contents

Page 1

... X 72 Bit (512MB) 240-Pin DDR2 Registered RDIMM ECC (PC2-3200) 1 Rank x 8; RoHS Compliant ,Lead Free GENERAL DESCRIPTION The SL72P8M64M8M-A05AY(W 64M x 72 bit (512MB) 240-pin Double Data Rate 2 (DDR2) Registered Dual In-line Memory Module (RDIMM) with data ECC support and optional address/command parity support ...

Page 2

... SL72P8M64M8M-A05AY(W)U DIMENSIONS (Board No. 1111) Units are in millimeters (inches). All dimensions are typical unless otherwise specified. 2X 0.157 (4.00) 0.700 (17.80) 0.394 2.48 (63.0) (10.0) 0.039 (1.0) 5.250 (133.35) EEPROM PLL 2.165 (55.0) 0.197 (5.0) 4.840 (123.0) 0.031 (0.80) 0.030 (0.76) R Document Part Number 61000-03657-105 November 2007 Page 2 240-PIN RDIMM 0 ...

Page 3

... SL72P8M64M8M-A05AY(W)U PIN CONFIGURATION (* = Not Used Optional Address/Command Parity support Active Low; Bold Line = Key) 240-Pin DIMM Front Pinout Pin Symbol Pin Symbol Pin Symbol Pin 1 VREF 31 DQ19 61 2 VSS 32 VSS 62 3 DQ0 33 DQ24 63 4 DQ1 34 DQ25 64 5 VSS 35 VSS 65 6 /DQS0 ...

Page 4

... SL72P8M64M8M-A05AY(W)U PIN CONFIGURATION continued (* = Not Used Optional Address/Command Parity Support Active Low) Pin Functions Symbol CK0, /CK0 CKE0 /S0 ODT0 /RAS, /CAS, /WE DM0-DM8 BA0-BA1 A0-A13, A14**, A15** DQ0-DQ63 CB0-CB7 DQS0-DQS17, /DQS0-/DQS17 SCL SA0-SA2 SDA /RESET NC RFU VDDQ VDD VSS VREF VDDSPD ...

Page 5

... SL72P8M64M8M-A05AY(W)U FUNCTIONAL BLOCK DIAGRAM /rS0 DQS0 /DQS0 DM0,DQS9 NC,/DQS9 DM, NU, /CS DQS /DQS RDQS /RDQS DQ0 DQ0 DQ1 DQ1 DQ2 DQ2 DDR2 DQ3 DQ3 SDRAM DQ4 DQ4 U0 DQ5 DQ5 DQ6 DQ6 DQ7 DQ7 DQS1 /DQS1 DM1,DQS10 NC,/DQS10 NU, DM, /CS DQS /DQS RDQS /RDQS ...

Page 6

... SL72P8M64M8M-A05AY(W)U SERIAL PRESENCE DETECT INFORMATION 2 Serial PD Interface Protocol Current sink capability of SDA driver <=3mA; Maximum clock frequency: 100 KHz Byte Description 0 Number of SPD Bytes Used by STEC 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly ...

Page 7

... SL72P8M64M8M-A05AY(W)U SERIAL PRESENCE DETECT INFORMATION Byte Description 45 SDRAM Device Max Read Data Hold Skew Factor, tQHS 46 PLL Relock Time 47-61 Reserved 62 SPD Revision 63 Checksum For Bytes 0-62 64 Manufacturer’s JEDEC ID Code 65 Man. JEDEC ID code (continued) 66-71 Reserved 72 Manufacturing Location 73-90 Module Part Number (ASCII) ...

Page 8

... SL72P8M64M8M-A05AY(W)U ABSOLUTE MAXIMUM DC RATINGS Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional Operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods may affect device reliability. Symbol Parameter VDD VDD Supply Voltage Relative to VSS ...

Page 9

... SL72P8M64M8M-A05AY(W)U RECOMMENDED DC OPERATING CONDITIONS All voltages referenced to VSS. Symbol Parameter VDD Supply Voltage VDDL VDDL Supply Voltage VDDQ I/O Supply Voltage VREF I/O Reference Voltage VTT I/O Termination Voltage (system) Notes: 1. VDD and VDDQ must track each other. VDDQ must be less than or equal to VDD. ...

Page 10

... SL72P8M64M8M-A05AY(W)U INPUT ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS Note: Values shown at DRAM inputs. For values at Register and PLL inputs, refer to the tables at the end of the document. Input DC Logic Levels All voltages referenced to VSS. Symbol Parameter VIH(DC) Input High (Logic 1) Voltage VIL(DC) Input Low (Logic 0) Voltage Input AC Logic Levels All voltages referenced to VSS ...

Page 11

... SL72P8M64M8M-A05AY(W)U IDD SPECIFICATIONS AND CONDITIONS IDD specifications are tested after the device is properly initialized. Recommended Operating Temperature. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/ 2. Input slew rate is specified by AC Parametric Test Conditions. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DQS, and /DQS ...

Page 12

... SL72P8M64M8M-A05AY(W)U IDD SPECIFICATIONS AND CONDITIONS Symbol—Parameter/Condition IDD0—Operating one bank active-precharge current; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. IDD1—Operating one bank active-read-precharge current; ...

Page 13

... SL72P8M64M8M-A05AY(W)U CAPACITANCE Vdd = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS 100 MHz, Recommended Operating Temperature, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.1V; DM input is grouped with I/O pins because DM and the I/O pins are matched in loading. Parameter Input Capacitance: CK, /CK (PLL Inputs) (5pF adder for board) ...

Page 14

... SL72P8M64M8M-A05AY(W)U AC OPERATING CONDITIONS AC Characteristics Parameter Command and Address Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time ...

Page 15

... SL72P8M64M8M-A05AY(W)U NOTES 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: ...

Page 16

... SL72P8M64M8M-A05AY(W)U NOTES (continued) 21. READS AND WRITES WITH AUTO PRECHARGE are allowed to be issued before tRAS (MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM devices. 22. VIL/VIH DDR2 overshoot/undershoot. REFER TO the 256Mb, 512Mb, or 1Gb DDR2 SDRAM data sheet for more detail. 23. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period ...

Page 17

... SL72P8M64M8M-A05AY(W)U REGISTER ELECTRICAL CHARACTERISTICS Recommended Operating Temperature Range; VDD=VDDQ=+1.8V ±0.1V unless otherwise stated. Symbol Parameters Conditions VIH(DC) DC High-Level Input SSTL_18 Voltage for Addr/Ctrl/Cmd VIL(DC) DC Low-Level Input SSTL_18 Voltage for Addr/Ctrl/Cmd VIH(AC) AC High-Level Input SSTL_18 Voltage for Addr/Ctrl/Cmd VIL(AC) AC Low-Level Input ...

Page 18

... SL72P8M64M8M-A05AY(W)U PLL CLOCK DRIVER ELECTRICAL CHARACTERISTICS Recommended Operating Temperature Range; AVDDQ = VDDQ = +1.8V ±0.1V unless otherwise stated. Symbol Parameters VIH DC High-Level Input Voltage for /RESET LVCMOS VIL DC Low-Level Input Voltage for /RESET LVCMOS VIN Input Voltage Limits for CK, /CK, /RESET VIH ...

Page 19

... SL72P8M64M8M-A05AY(W)U REVISION HISTORY Rev. Change Description from Previous Revision -101 09/08/2005. Initial release. -102 04/27/2006. Address/CMD parity optional. -103 01/26/2006. Added “W” designator to part number suffix and ordering information to indicate that the product can be ordered with industrial operating temperature grade components. ...

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