SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 14

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
AC OPERATING CONDITIONS
AC Characteristics
Parameter
Command and Address
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
Address and control input setup time
Address and control input hold time
/CAS to /CAS command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE BANK a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate Period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,/CK uncertainty
Self Refresh
REFRESH to Active or REFRESH command interval
Average periodic refresh interval
Exit self refresh to non-READ command
Exit self refresh to READ command
Exit self refresh timing reference
ODT
ODT turn-on delay
ODT turn-on
ODT turn-off delay
ODT turn-off
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
ODT to power-down entry latency
ODT power-down exit latency
Power Down
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
Exit precharge power-down to any non-READ command
CKE minimum high/low time
(continued)
Document Part Number 61000-03657-105 November 2007 Page 14
Symbol
tAONPD
tXARDS
tDELAY
tAOFPD
tAOND
tAOFD
tXSNR
tXSRD
tANPD
tAXPD
tXARD
tFAW
tWTR
tAON
tCCD
tRRD
tRCD
tRAS
tDAL
tMRD
tREFI
tISXR
tRPA
tRFC
tCKE
tIPW
tRTP
tAOF
tWR
tISa
tIHa
tISb
tIHb
tRC
tRP
tXP
tIS+tCK+tIH tIS+tCK+tIH
tRFC(MIN)+10
tWR + tRP
tRP + tCK
tAC(MIN)+
tAC(MIN)+
tAC(MIN)
tAC MIN
6 - AL
0.475
Min
0.35
37.5
0.35
105
200
0.6
0.6
0.6
7.5
7.5
2.5
55
15
15
10
15
40
2
2
2
3
8
2
2
2
2
3
DDR2-400
tAC(MAX)+0.6
tAC(MAX)+1
2.5xtCK+tAC
2xtCK+tAC
70,000
70,000
(MAX)+1
(MAX)+1
Max
7.8
2.5
2
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
240-PIN RDIMM
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
Notes
21, 34
24, 28
6, 22
6, 22
6, 22
6, 22
6, 30
34
28
31
28
23
28
32
32
29
14
14
26
27
35