LC51024MV-52F484C Lattice, LC51024MV-52F484C Datasheet - Page 19

• Manufacturer Part Number: LC51024MV-52F484C
• Manufacturer: Lattice

Lattice Semiconductor
Table 12. ispXPLD 5000MX Supported I/O Standards
Table 13. Differential Interface Standard Support
Control, Clock, sysCONFIG and JTAG Signals
Global clock pins support the same sysIO standards as general purpose I/O. When required the V
derived from the adjacent bank. When differential standards are supported two adjacent clock pins are paired to
form the input. The TOE, PROGRAM, CFG0 and DONE pins of the ispXPLD 5000MX device are the only pins that
do not have sysIO capabilities. The JTAG TAP pins support only LVCMOS 3.3, 2.5 and 1.8V standards. The voltage
is controlled by V
voltage of the device. The global reset global output enable pins are associated with Bank 2 and support all of the
sysIO standards.
Hotsocketing
The I/O on the ispXPLD 5000MX devices are well suited for those applications that require hot socketing capability,
when configured as LVCMOS or LVTTL. Hot socketing a device requires that the device, when powered down, can
tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the
powered-down device be minimal on active signals.
Programmable Drive Strength
The drive strength of I/Os that are programmed as LVCMOS is tightly controlled and can be programmed to a vari-
ety of different values. Thus the impedance an output driver can be closely match to the characteristic impedance
of the line it is driving. This allows users to eliminate the need for external series termination resistors.
LVTTL
LVCMOS-3.3
LVCMOS-2.5
LVCMOS-1.8
PCI 3.3V
AGP-1X
SSTL3, Class I & II
SSTL2, Class I & II
CTT 3.3
CTT 2.5
HSTL, Class I
HSTL, Class III
HSTL, Class IV
GTL+
LVPECL, Differential
LVDS
sysIO Standard
LVDS
LVPECL
1. For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines for Lattice Devices, available at
www.latticesemi.com.
CCJ.
These pins only support the LVTTL and LVCMOS standards applicable to the power supply
Driver
Receiver
Driver
Receiver
Nominal V
2.5V, 3.3V
2.5V, 3.3V
3.3V
3.3V
2.5V
1.8V
3.3V
3.3V
3.3V
2.5V
3.3V
2.5V
1.5V
1.5V
1.5V
N/A
CCO
Supported
Supported with standard termination
Supported with external resistor network
Supported with termination
1
19
Nominal V
ispXPLD 5000MX Family Data Sheet
1.25V
1.25V
0.75V
1.5V
1.5V
0.9V
0.9V
1.0V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
sysIO Buffer
REF
Nominal V
1.25V
1.25V
0.75V
0.75V
0.75V
1.5V
1.5V
1.5V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
TT
signal is