LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 102

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
6.3.13
BITS
31:14
13-12
10
11
9
8
7
6
DESCRIPTION
RESERVED
Power Management Mode (PM_MODE)
the appropriate Power Management mode. Special care must be taken when
modifying these bits.
Encoding:
00b – D0 (normal operation)
01b – D1 (wake-up frame and magic packet detection are enabled)
10b – D2 (can perform energy detect)
11b – RESERVED - Do not set in this mode
Note:
RESERVED
PHY Reset (PHY_RST) – Writing a ‘1’ to this bit resets the PHY. The internal
logic automatically holds the PHY reset for a minimum of 100us. When the
PHY is released from reset, this bit is automatically cleared. All writes to this
bit are ignored while this bit is high.
Wake-On-Lan Enable (WOL_EN) – When set, the PME signal (if enabled
with PME_EN) will be asserted in accordance with the PME_IND bit upon a
WOL event. When set, the PME_INT will also be asserted upon a WOL
event, regardless of the setting of the PME_EN bit.
Energy-Detect Enable (ED_EN) - When set, the PME signal (if enabled with
PME_EN) will be asserted in accordance with the PME_IND bit upon an
Energy-Detect event. When set, the PME_INT will also be asserted upon an
Energy Detect event, regardless of the setting of the PME_EN bit.
RESERVED
PME Buffer Type (PME_TYPE) – When cleared, enables PME to function as
an open-drain buffer for use in a Wired-Or configuration. When set, the PME
output is a Push-Pull driver. When configured as an open-drain output the
PME_POL field is ignored, and the output is always active low.
PMT_CTRL— Power Management Control Register
This register controls the Power Management features. This register can be read while the
LAN9118
Note: The LAN9118 must always be read at least once after power-up, reset, or upon return from a
Offset:
When the LAN9118 is in a any of the reduced power modes, a write
of any data to the BYTE_TEST register will wake-up the device. DO
NOT PERFORM WRITES TO OTHER ADDRRESSES while the
READY bit in this register is cleared.
power-saving state or write operations will not function.
is in a power saving mode.
84h
DATASHEET
–
These bits set the LAN9118 into
102
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
32 bits
TYPE
NASR
R/W
R/W
R/W
RO
RO
RO
SC
SC
SMSC LAN9118
DEFAULT
Datasheet
00b
0b
0b
0b
0b
-
-
-