LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 136

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
6.5.1
BITS
6-0
15
14
13
12
11
10
9
8
7
DESCRIPTION
Reset. 1 = software reset. Bit is self-clearing. For best results, when setting
this bit do not set other bits in this register.
Loopback. 1 = loopback mode, 0 = normal operation
Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is
enabled (0.12 = 1).
Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides
0.13 and 0.8) 0 = disable auto-negotiate process.
Power Down. 1 = General power down-mode, 0 = normal operation.
Note:
Reserved
Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal
operation. Bit is self-clearing.
Duplex Mode. 1 = full duplex, 0 = half duplex. Ignored if Auto Negotiation
is enabled (0.12 = 1).
Collision Test. 1 = enable COL test, 0 = disable COL test
Reserved
Basic Control Register
Note 6.1
Index (In Decimal):
After this bit is cleared, the PHY may auto-negotiate with it's
partner station. This process may take a few seconds to complete.
Once auto-negotiation is complete, bit 5 of the PHY's Basic Status
Register will be set.
This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the
pin description section for more details
0
DATASHEET
136
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
16-bits
RW/SC
RW/SC
TYPE
RW
RW
RW
RW
RW
RW
RO
RO
See Note 6.1
See Note 6.1
SMSC LAN9118
DEFAULT
Below
Below
Datasheet
0
0
0
0
0
0
0
0