LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 152

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
7.1.2
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9118, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in the table below. The host processor is required to
wait the specified period of time between read operations of specific combinations of resources. The
wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.The table below also shows the number of dummy reads that are
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
RX Status FIFO
TX Status FIFO
RX Data FIFO
READING...
RX_DROP
AFTER
Table 7.2 Read after Read Timing Rules
WAIT FOR THIS
MANY NS…
135
180
135
135
DATASHEET
152
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
(ASSUMING Tcycle OF
OR PERFORM THIS
MANY READS OF
BYTE_TEST…
45NS)
3
3
3
4
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
READING...
RX_DROP
BEFORE
SMSC LAN9118
Datasheet