AD7233BN Analog Devices Inc, AD7233BN Datasheet - Page 7

• Manufacturer Part Number: AD7233BN
• Description: IC DAC 12BIT SRL W/AMP 8-DIP
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD7233BN

• Rohs Status: RoHS non-compliant
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 168mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)

MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7233 is via a serial bus that
uses standard protocol compatible with DSP processors and
microcontrollers. The communications channel requires a
three-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD7233 requires a 16-bit data
word with data valid on the falling edge of SCLK. For all of the
interfaces, the DAC update may be done automatically when all
the data is clocked in or it may done under control of LDAC.
Figures 5 to 8 show the AD7233 configured for interfacing to a
number of popular DSP processors and microcontrollers.
AD7233–ADSP-2101/ADSP-2102 Interface
Figure 5 shows a serial interface between the AD7233 and the
ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/
ADSP-2102 contains two serial ports, and either port may be
used in the interface. The data transfer is initiated by TFS going
low. Data from the ADSP-2101/ADSP-2102 is clocked into the
AD7233 on the falling edge of SCLK. When the data transfer is
complete TFS is taken high. In the interface shown the DAC is
updated using an external timer which generates an LDAC pulse.
This could also be done using a control or decoded address line
from the processor. Alternatively, the LDAC input could be
hardwired low, and in this case the automatic update mode is
selected whereby the DAC update takes place automatically on
the 16th falling edge of SCLK.
AD7233-DSP56000 Interface
A serial interface between the AD7233 and the DSP56000 is
shown in Figure 6. The DSP56000 is configured for Normal Mode
Asynchronous operation with Gated Clock. It is also set up for a
16-bit word with SCK and SC2 as outputs and the FSL control bit
set to a 0. SCK is internally generated on the DSP56000 and
applied to the AD7233 SCLK input. Data from the DSP56000 is
valid on the falling edge of SCK. The SC2 output provides the
framing pulse for valid data. This line must be inverted before
being applied to the SYNC input of the AD7233.
The LDAC input of the AD7233 is connected to GND so the
update of the DAC latch takes place automatically on the 16th
falling edge of SCLK. An external timer could also be used as in
the previous interface if an external update is required.
ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-2101/
ADSP-2102
SCLK
TFS
DT
TIMER
LDAC
SYNC
SCLK
SDIN
AD7233
AD7233–87C51 Interface
A serial interface between the AD7233 and the 87C51 micro-
controller is shown in Figure 7. TXD of the 87C51 drives
SCLK of the AD7233 while RXD drives the serial data line of
the part. The SYNC signal is derived from the port line P3.3.
The 87C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the don’t care bits are the first to be transmitted to the AD7233
and the last bit to be sent is the LSB of the word to be loaded to
the AD7233. When data is to be transmitted to the part, P3.3 is
taken low. Data on RXD is valid on the falling edge of TXD.
The 87C51 transmits its serial data in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. To load data
to the AD7233, P3.3 is kept low after the first eight bits are
transferred and a second byte of data is then transferred serially
to the AD7233. When the second serial transfer is complete, the
P3.3 line is taken high.
Figure 7 shows the LDAC input of the AD7233 hardwired low.
As a result, the DAC latch and the analog output will be updated
on the sixteenth falling edge of TXD after the SYNC signal for
the DAC has gone low. Alternatively, the scheme used in previ-
ous interfaces, whereby the LDAC input is driven from a timer,
can be used.
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
DSP56000
87C51
P3.3
RXD
TXD
SCK
STD
SC2
LDAC
SYNC
SCLK
SDIN
LDAC
SCLK
SDIN
SYNC
AD7233
AD7233
AD7233