AD7233BN Analog Devices Inc, AD7233BN Datasheet - Page 8

• Manufacturer Part Number: AD7233BN
• Description: IC DAC 12BIT SRL W/AMP 8-DIP
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD7233BN

• Rohs Status: RoHS non-compliant
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 168mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)

AD7233–Revision History
Location
Data Sheet changed from REV. A to REV. B.
B Version column added to Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
AD7233
AD7233-68HC11 Interface
Figure 8 shows a serial interface between the AD7233 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7233 while the MOSI output drives the serial data line.
The SYNC signal is derived from a port line (PC7 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a
1. When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. To load data to the AD7233, PC7 is kept
low after the first eight bits are transferred and a second byte of
data is then transferred serially to the AD7233. When the sec-
ond serial transfer is complete, the PC7 line is taken high. Fig-
ure 8 shows the LDAC input of the AD7233 hardwired low.
As a result, the DAC latch and the analog output of the DAC
0.160 (4.06)
0.115 (2.93)
(5.33)
0.210
MAX
PIN 1
0.022 (0.558)
0.014 (0.356)
Dimensions shown in inches and (mm).
8
0.430 (10.92)
0.348 (8.84)
0.100 (2.54)
1
OUTLINE DIMENSIONS
Plastic DIP (N-8) Package
BSC
0.070 (1.77)
0.045 (1.15)
5
4
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
SEATING
PLANE
0.130
(3.30)
MIN
will be updated on the sixteenth falling edge of SCK after the
respective SYNC signal has gone low. Alternatively, the scheme
used in previous interfaces, whereby the LDAC input is driven
from a timer, can be used.
ADDITIONAL PINS OMITTED FOR CLARITY
0.325 (8.25)
0.300 (7.62)
68HC11
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
MOSI
SCK
PC7
LDAC
SYNC
SCLK
SDIN
AD7233
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