AD5382BST-5 Analog Devices Inc, AD5382BST-5 Datasheet
AD5382BST-5
Specifications of AD5382BST-5
Related parts for AD5382BST-5
AD5382BST-5 Summary of contents
Page 1
FEATURES Guaranteed monotonic INL error: ±4 LSB max On-chip 1.25 V/2 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode Package type: 100-lead LQFP (14 mm × 14 mm) User interfaces: Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, featuring ...
Page 2
AD5382 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications ..................................................................................... 4 AD5382-5 Specifications ............................................................. 4 AD5382-3 Specifications ............................................................. 6 AC Characteristics ........................................................................ 7 Timing Characteristics ..................................................................... 8 SPI-, QSPI-, MICROWIRE-, or DSP-Compatible Serial Interface ......................................................................................... Serial ...
Page 3
GENERAL DESCRIPTION The AD5382 is a complete, single-supply, 32-channel, 14-bit DAC available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5382 includes an internal software-selectable 1. ppm/°C ...
Page 4
AD5382 SPECIFICATIONS AD5382-5 SPECIFICATIONS AVDD = 4 5.5 V; DVDD = 2 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V; all specifications T unless otherwise noted. Table 3. Parameter ACCURACY Resolution ...
Page 5
Parameter LOGIC INPUTS (SDA, SCL ONLY Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis HYST C , Input Capacitance IN Glitch Rejection 3 LOGIC OUTPUTS (BUSY, ...
Page 6
AD5382 AD5382-3 SPECIFICATIONS AVDD = 2 3.6 V; DVDD = 2 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications T unless otherwise noted. Table 4. Parameter ACCURACY Resolution 2 ...
Page 7
Parameter 3 LOGIC OUTPUTS (BUSY, SDO Output Low Voltage Output High Voltage OH High Impedance Leakage Current High Impedance Output Capacitance 3 LOGIC OUTPUT (SDA Output Low Voltage OL Three-State Leakage Current Three-State ...
Page 8
AD5382 TIMING CHARACTERISTICS SPI-, QSPI-, MICROWIRE-, OR DSP-COMPATIBLE SERIAL INTERFACE DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless ...
Page 9
SCLK SYNC DIN DB23 BUSY 1 LDAC VOUT1 2 LDAC VOUT2 t 18 CLR VOUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 3. Serial Interface ...
Page 10
AD5382 SERIAL INTERFACE DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table 7. ...
Page 11
PARALLEL INTERFACE DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications Tmin to Tmax, unless otherwise noted. Table ...
Page 12
AD5382 REG0, REG1, A4...A0 DB13...DB0 BUSY LDAC VOUT1 LDAC VOUT2 CLR VOUT ...
Page 13
ABSOLUTE MAXIMUM RATINGS 25°C, unless otherwise noted . A Table 9. Parameter Rating AVDD to AGND –0 DVDD to DGND –0 Digital Inputs to DGND –0 DVDD ...
Page 14
AD5382 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FIFO EN 1 CLR 2 VOUT24 3 4 VOUT25 5 VOUT26 6 VOUT27 SIGNAL_GND4 7 DAC_GND4 8 AGND4 9 AVDD4 10 VOUT28 11 VOUT29 12 VOUT30 13 VOUT31 14 REFGND 15 REFOUT/REFIN 16 SIGNAL_GND1 ...
Page 15
Mnemonic Function MON_OUT Monitor Output. When the monitor function is enabled, this pin acts as the output of a 36-to-1 channel multiplexer that can be programmed to multiplex one of Channels any of the monitor input ...
Page 16
AD5382 Mnemonic Function PD Power Down (Level Sensitive, Active High used to place the device in to low power mode where the device consumes 2 μA AIDD and 20 μA DIDD. In power-down mode, all internal analog circuitry ...
Page 17
TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero-scale error and full-scale error, and ...
Page 18
AD5382 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 AVDD = DVDD = 5.5V V 1.5 T 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 INPUT CODE Figure 9. Typical AD5382-5 INL Plot 2.539 AVDD = DVDD = 5V 2.538 V = ...
Page 19
AI (mA) DD Figure 15. AI Histogram 0.4 0.5 0.6 0.7 0.8 DI (mA) DD Figure 16. DI Histogram DD WR BUSY AVDD ...
Page 20
AD5382 6 FULL SCALE 5 AVDD = DVDD = 5V 3/4 SCALE 4 MIDSCALE 3 2 1/4 SCALE 1 ZERO SCALE 0 –1 –40 –20 –10 –5 – CURRENT (mA) Figure 21. AD5382-5 Output Amplifier Source and Sink ...
Page 21
FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5382 is a complete, single-supply, 32-channel voltage output DAC that offers 14-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an ...
Page 22
AD5382 Table 14. Gain Data Format (REG1 = 0, REG0 = 1) DB13 to DB0 Gain Factor 11 1111 1111 1110 1 10 1111 1111 1110 0.75 01 1111 1111 1110 0.5 00 0111 1111 1110 0.25 00 0000 0000 ...
Page 23
Table 16. Control Register Contents MSB CR13 CR12 CR11 CR10 Control Register Write/Read REG1 = REG0 = 0, A4–A0 = 01100 status determines if the operation is a write ( read (R/ W ...
Page 24
AD5382 Table 18. AD5382 Channel Monitor Decoding REG1 REG0 ...
Page 25
HARDWARE FUNCTIONS RESET FUNCTION Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. Reset is a negative edge- sensitive input. The default corresponds full scale and ...
Page 26
AD5382 AD5382 INTERFACES The AD5382 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed to be either SPI-, DSP-, MICROWIRE SER/ PAR pin selects parallel and serial interface modes serial mode, the ...
Page 27
Daisy-Chain Mode For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. By connecting the ...
Page 28
AD5382 SERIAL INTERFACE 2 The AD5382 features an I C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5382 and the master at ...
Page 29
SCL SDA START COND BY MASTER ADDRESS BYTE SCL REG1 REG0 MSB SDA MOST SIGNIFICANT BYTE SCL SDA START COND BY MASTER ADDRESS BYTE SCL SDA REG1 REG0 MSB MOST ...
Page 30
AD5382 2-Byte Mode Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is required only once, and the pointer address pointer is configured for auto- increment or burst mode. The user must begin with ...
Page 31
MICROPROCESSOR INTERFACING Parallel Interface The AD5382 can be interfaced to a variety of 16-bit microcon- trollers or DSP processors. Figure 35 shows the AD5382 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are ...
Page 32
AD5382 AD5382 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the Clock Polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller ...
Page 33
APPLICATION INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5382 is mounted should ...
Page 34
AD5382 MONITOR FUNCTION The AD5382 channel monitor function consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be enabled in ...
Page 35
INPUT INPUT DATA REGISTER A/B 0.01μF REFOUT/REFIN 14-BIT DAC 14-BIT DAC AD5382 THERMAL MONITOR FUNCTION The AD5382 contains a temperature shutdown function to protect the chip if multiple outputs are shorted. The short- circuit current of each output amplifier is ...
Page 36
AD5382 OPTICAL ATTENUATORS Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5382 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (VOA), and optical add-drop multiplexers ...
Page 37
... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1 Model Resolution Temperature Range AD5382BSTZ-3 14 Bits –40°C to +85°C AD5382BSTZ-5 14 Bits –40°C to +85°C EVAL-AD5382EBZ RoHS Compliant Part. 16.00 BSC SQ 1.60 MAX 14.00 BSC SQ 0.75 100 1 0.60 0.45 PIN 1 ...
Page 38
AD5382 NOTES Rev Page ...
Page 39
NOTES Rev Page AD5382 ...
Page 40
AD5382 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). © 2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03733–0–4/10(B) Rev. B ...