AD5382BST-5 Analog Devices Inc, AD5382BST-5 Datasheet - Page 27

• Manufacturer Part Number: AD5382BST-5
• Description: IC DAC 14BIT 32CH 5V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5382BST-5

• Design Resources: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011) AD5382 Channel Monitor Function (CN0012)
• Settling Time: 8µs
• Number Of Bits: 14
• Data Interface: Serial, Parallel
• Number Of Converters: 32
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 65mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5382EB - BOARD EVAL FOR AD5382
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Daisy-Chain Mode
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
By connecting the DCEN (daisy-chain enable) pin high, daisy-
chain mode is enabled. The first falling edge of SYNC starts the
write cycle. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears
on the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the DIN input on the next device in the
chain, a multidevice interface is constructed. Twenty-four clock
pulses are required for each device in the system. Therefore, the
total number of clock cycles must equal 24N, where N is the
total number of AD538x devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy-chain and prevents further data from being clocked into
the input shift register.
If the SYNC is taken high before 24 clocks are clocked into the
part, this is considered a bad frame and the data is discarded.
The serial clock can be either a continuous or a gated clock. A
continuous SCLK source can be used only if SYNC can be held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
SYNC
SCLK
SDO
DIN
INPUT WORD SPECIFIES REGISTER TO BE READ
DB23
DB23
UNDEFINED
Figure 30. Serial Readback Operation
24
DB0
DB0
Rev. B | Page 27 of 40
DB23
DB23
SELECTED REGISTER DATA CLOCKED OUT
Readback Mode
Readback mode is invoked by setting the R/ W bit = 1 in the
serial input register write. With R/ W = 1, Bits A4 to A0, in
association with Bits REG1 and REG0, select the register to be
read. The remaining data bits in the write sequence are don’t
cares. During the next SPI write, the data appearing on the SDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on SDO.
Figure 30 shows the readback sequence. For example, to read
back the m register of Channel 0 on the AD5382, the following
sequence should be implemented. First, write 0x404XXX to the
AD5382 input register. This configures the AD5382 for read
mode with the m register of Channel 0 selected. Data Bits DB13
to DB0 are don’t cares. Follow this with a second write, a NOP
condition, 0x000000. During this write, the data from the m
register is clocked out on the DOUT line, that is, data clocked
out contains the data from the m register in Bits DB13 to DB0,
and the top 10 bits contain the address information as
previously written. In readback mode, the SYNC signal must
frame the data. Data is clocked out on the rising edge of SCLK
and is valid on the falling edge of the SCLK signal. If the SCLK
idles high between the write and read operations of a readback
operation, the first bit of data is clocked out on the falling edge
of SYNC .
NOP CONDITION
48
DB0
DB0
AD5382