ATF750LVC-15PC Atmel, ATF750LVC-15PC Datasheet - Page 10

• Manufacturer Part Number: ATF750LVC-15PC
• Description: IC CPLD 15NS 24DIP
• Manufacturer: Atmel
• Series: ATF750LVCr

Specifications of ATF750LVC-15PC

• Programmable Type: In System Programmable (min 1K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 5.25 V
• Number Of Macrocells: 10
• Number Of I /o: 10
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Voltage: 3.3V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: ATF750LVC15PC

20. Using the ATF750LVC’s Many Advanced Features
21. Synchronous Preset and Asynchronous Reset
22. Security Fuse Usage
10
ATF750LVC
The ATF750LVC’s advanced flexibility packs more usable gates into 24-pins than any other
logic device. The ATF750LVCs start with the popular 22V10 architecture, and add several
enhanced features:
One synchronous preset line is provided for all 20 registers in the ATF750LVC. The appropri-
ate input signals to cause the internal clocks to go to a high state must be received during a
synchronous preset. Appropriate setup and hold times must be met, as shown in the switching
waveform diagram.
An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and
slave halves of the flip-flops are reset when the input signals received force the internal resets
high.
A single fuse is provided to prevent unauthorized copying of the ATF750LVC fuse patterns.
Once the security fuse is programmed, all fuses will appear programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
• Selectable D- and T-type Registers
• Selectable Asynchronous Clocks
• A Full Bank of Ten More Registers
• Independent I/O Pin and Feedback Paths
Each ATF750LVC flip-flop can be individually configured as either D- or T-type. Using the
T-type configuration, JK and SR flip-flops are also easily created. These options allow more
efficient product term usage.
Each of the ATF750LVC’s flip-flops may be clocked by its own clock product term or
directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use
the same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.
The ATF750LVC provides two flip-flops per output logic cell for a total of 20. Each register
has its own sum term, its own reset term and its own clock term.
Each I/O pin on the ATF750LVC has a dedicated input path. Each of the 20 registers has
its own feedback terms into the array as well. This feature, combined with individual
product terms for each I/O’s output enable, facilitates true bi-directional I/O design.
1447F–PLD–11/08