EPM7064SLC84-10N Altera, EPM7064SLC84-10N Datasheet

Specifications of EPM7064SLC84-10N
Programmable Type	In System Programmable	Delay Time Tpd(1) Max	10.0ns
Voltage Supply - Internal	4.75 V ~ 5.25 V	Number Of Logic Elements/blocks	4
Number Of Macrocells	64	Number Of Gates	1250
Number Of I /o	68	Operating Temperature	0°C ~ 70°C
Mounting Type	Surface Mount	Package / Case	84-PLCC
Voltage	5V	Memory Type	EEPROM
Number Of Logic Elements/cells	4	Lead Free Status / RoHS Status	Lead free / RoHS Compliant
Features	-	Other names	544-2015 EPM7064SLC84-10N

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MAX 7000 Programmable Logic Device Family Data Sheet

Programmable Interconnect Array

Logic is routed between LABs via the programmable interconnect array

(PIA). This global bus is a programmable path that connects any signal

source to any destination on the device. All MAX 7000 dedicated inputs,

I/O pins, and macrocell outputs feed the PIA, which makes the signals

available throughout the entire device. Only the signals required by each

LAB are actually routed from the PIA into the LAB.

the PIA signals are routed into the LAB. An EEPROM cell controls one

input to a 2-input AND gate, which selects a PIA signal to drive into the

LAB.

Figure 7. PIA Routing

While the routing delays of channel-based routing schemes in masked or

FPGAs are cumulative, variable, and path-dependent, the MAX 7000 PIA

has a fixed delay. The PIA thus eliminates skew between signals and

makes timing performance easy to predict.

I/O Control Blocks

The I/O control block allows each I/O pin to be individually configured

for input, output, or bidirectional operation. All I/O pins have a tri-state

buffer that is individually controlled by one of the global output enable

signals or directly connected to ground or V

control block for the MAX 7000 family. The I/O control block of EPM7032,

EPM7064, and EPM7096 devices has two global output enable signals that

are driven by two dedicated active-low output enable pins (OE1 and OE2).

The I/O control block of MAX 7000E and MAX 7000S devices has six

global output enable signals that are driven by the true or complement of

two output enable signals, a subset of the I/O pins, or a subset of the I/O

macrocells.

PIA Signals

Figure 7

shows how

To LAB

Figure 8

shows the I/O

Altera Corporation

EPM7064SLC84-10N