AN209 Altera Corporation, AN209 Datasheet

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AN209

Manufacturer Part Number
AN209
Description
Manufacturer
Altera Corporation
Datasheet
Introduction
Altera Corporation
AN-209-2.0
November 2002, ver. 2.0
Signal integrity is crucial in high-speed digital designs because of
increased system speeds and clock edge rates. Designers must properly
terminate single-ended and differential signals to achieve signal integrity.
Traditionally, designers use on-board termination resistors to achieve
proper signal termination. However, these resistors take up significant
board space and can cause signal reflections (stub effects). These
reflections normally occur when a termination resistor is too far away
from the transmission line it terminates.
Terminator
prevent reflections, improving signal integrity. To address these issues,
Stratix and Stratix GX devices have driver impedance matching and on-
chip termination circuitry. Terminator technology includes series
termination, impedance matching, parallel termination for single-ended
I/O standards (e.g., HSTL and SSTL-2), and differential termination.
Termination resistors are adjacent to the buffers on the device, thereby
eliminating stub effects. Terminator technology minimizes the need for a
cumbersome external resistor network, thereby easing board routing and
saving board space.
with external termination and with Terminator technology.
This application note covers various Terminator technology types
supported by Stratix and Stratix GX devices as well as power
management.
Figure 1. Device Footprint Comparison with & without Terminator Technology
Termination
Resistors
TM
technology in Stratix
Figure 1
Termination
External
With
Technology in Stratix &
shows a footprint comparison of a device
TM
Stratix GX Devices
and Stratix GX devices helps
Using Terminator
Technology
Terminator
With
Application Note 209
Reference
Resistors
1

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AN209 Summary of contents

Page 1

... November 2002, ver. 2.0 Introduction Altera Corporation AN-209-2.0 Signal integrity is crucial in high-speed digital designs because of increased system speeds and clock edge rates. Designers must properly terminate single-ended and differential signals to achieve signal integrity. Traditionally, designers use on-board termination resistors to achieve proper signal termination. However, these resistors take up significant board space and can cause signal reflections (stub effects) ...

Page 2

... LVTTL/LVCMOS LVTTL/LVCMOS and R ) per CCIO ) and SSTL-3 class II (3.3-V V CCIO and V voltages. You can CCIO REF AN 201: Using Selectable I/O Standards V CCIO 3.3 3.3 2.5 2.5 3.3 2.5 1.8 Altera Corporation bank are used ; R is CCIO DN ), use CCIO in an I/O CCIO (V) ...

Page 3

... R s Parallel Termination ( Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Impedance Matching The impedance of the output driver is matched with the transmission line impedance. Stratix and Stratix GX output buffers can match output impedance to either This impedance matching results in properly terminated signals, improving signal integrity. This feature is supported by all Stratix device I/O pins ...

Page 4

... V Figure 4 shows the connection scheme for these particular I/O standards. Receiver with Terminator Technology Parallel Termination REF Parallel Parallel Termination ( N/A 50 for parallel termination (V) CCIO 3.3 3.3 2.5 2.5 1.5 1.5 3.3 3.3 3.3 Altera Corporation ...

Page 5

... R S Differential Termination ( Figure 5. Terminator Technology Differential Termination Differential Transmitter Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices External Resistor Provided by User Terminator technology supports on-chip differential termination for source-synchronous LVDS signalling. The differential termination resistors are adjacent to the differential input buffers on the device. This placement eliminates stub effects, improving the signal integrity of the serial link ...

Page 6

... Termination Type Impedance Matching Series Termination Parallel Termination Differential Termination Note to Table 3: ( the target on-chip impedance. 0 and the two dual pull-up resistor and pull-down resistor and DN Figure 6 below shows the reference V CCIO GND Note (1) ) Impedance ( 100 Not needed Altera Corporation for / ...

Page 7

... Power Analysis Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Terminator technology on-chip termination resistors increase the total current draw of the device. This increase in current draw occurs because the termination circuitry, which is normally external to the device, is now a part of the device. Make sure the device’s current consumption in a design does not exceed any device limits ...

Page 8

... S T1 N/A N/A 10 N/A 23 N/A 11 N/A 24 N/A (4) N/A N/A (4) N/A N/A N/A is the parallel termination resistor next to the input buffer. See T2 (2) Input Mode ( Note (1) V (V) CCIO 3.3 3.3 2.5 2.5 3.3 3.3 3.3 1.5 1.5 is the parallel T1 Altera Corporation ...

Page 9

... The CTT output buffer and HSTL class I output buffer do not draw any current due to the on-chip termination resistor for single-ended I/O pins, but they will still draw specified in the corresponding JEDEC specifications. Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices When using bidirectional pins, the total DC current draw by Terminator ...

Page 10

... Series Parallel Termination 16 N N/A 5 N/A 5 N/A 17 N/A 17 N/A 24 and R , per I/O bank shows a Stratix or Stratix GX device’s AN 201: Using Selectable I/O Standards in V (V) CCIO 3.3 2.5 2.5 2.5 3.3 3.3 1.5 1.5 3.3 3.3 3.3 Altera Corporation ...

Page 11

... Figure 7. Current Draw Limitation Guidelines Using Terminator Technology Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices I/O Pin Sequence of an I/O Bank VCC GND VCC GND VCC If the ten consecutive I/O pins exclude either R current draw limitations in thermally enhanced BGA packages cannot exceed 200 mA ...

Page 12

... In the above example, the total current draw for all ten consecutive I/O pins is more than 200 mA. Therefore, this case is not allowed and the Quartus II software generates an error message during design compilation. 6 for values and R UP and 7 for values): and mA) + (26 mA) = 218 mA both pins mA) + Altera Corporation ...

Page 13

... Design Tips Conclusion Revision History Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices The following is a list of design tips: Parallel termination is supported only on the top and bottom I/O banks. Series termination and impedance matching is supported on all the I/O banks. ...

Page 14

... Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...

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