XCR3128XL-7VQ100C Xilinx Inc, XCR3128XL-7VQ100C Datasheet - Page 3

• Manufacturer Part Number: XCR3128XL-7VQ100C
• Description: IC CPLD 128MCELL 3.3V HP 100VQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner XPLA3r

Specifications of XCR3128XL-7VQ100C

• Programmable Type: In System Programmable (min 1K program/erase cycles)
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 3000
• Number Of I /o: 84
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Features: Low Power
• Voltage: 3.3V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

AC Electrical Characteristics Over Recommended Operating Conditions
Internal Timing Parameters
DS016 (v2.6) March 31, 2006
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
T
T
T
T
T
T
T
T
T
T
T
T
f
T
T
T
T
T
T
Buffer Delays
T
T
T
T
T
Internal Register and Combinatorial Delays
T
T
T
SYSTEM
Symbol
APRPW
PD1
PD2
CO
SUF
SU1
SU2
H
WLH
PLH
R
L
CONFIG
INIT
POE
POD
PCO
PAO
OUT
IN
FIN
GCK
EN
LDI
SUI
HI
Symbol
(4)
(4)
(4)
Specifications measured with one output switching.
See the CoolRunner XPLA3 family data sheet (
See
These parameters guaranteed by design and/or characterization, not testing.
Typical current draw during configuration is 9 mA at 3.6V.
Output C
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
Figure 6
(4)
(4)
R
L
Propagation delay time (single p-term)
Propagation delay time (OR array)
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
Hold time
Global Clock pulse width (High or Low)
P-term clock pulse width
Asynchronous preset/reset pulse width (High or Low)
Input rise time
Input fall time
Maximum system frequency
Configuration time
ISP initialization time
P-term OE to output enabled
P-term OE to output disabled
P-term clock to output
P-term set/reset to output valid
= 5 pF.
Input buffer delay
Fast Input buffer delay
Global Clock buffer delay
Output buffer delay
Output buffer enable/disable delay
Latch transparent delay
Register setup time
Register hold time
for derating.
Parameter
(5)
Parameter
(1,2)
(6)
DS012
(3)
www.xilinx.com
) for recommended operating conditions.
Min.
1.0
0.3
-
-
-
-
-
-
-6
Min.
2.5
3.5
4.0
2.5
4.0
4.0
0
-
-
-
-
-
-
-
-
-
-
-
-
Max.
1.3
2.3
0.8
2.2
4.2
1.3
-
-
-6
Max.
175
100
100
5.5
6.0
4.0
7.5
7.5
7.0
8.0
20
20
-
-
-
-
-
-
-
Min.
1.0
0.5
-
-
-
-
-
-
Min.
3.0
4.3
4.8
3.0
5.0
5.0
0
-
-
-
-
-
-
-
-
-
-
-
-7
XCR3128XL 128 Macrocell CPLD
-7
Max.
1.6
3.0
1.0
2.7
5.0
1.6
-
-
Max.
119
100
100
7.0
7.5
5.0
9.3
9.3
8.3
9.3
20
20
-
-
-
-
-
-
-
Min.
1.2
0.7
Min.
-
-
-
-
-
-
3.0
5.4
6.3
4.0
6.0
6.0
0
-
-
-
-
-
-
-
-
-
-
-
-
-10
-10
Max.
(1,2)
2.2
3.1
1.3
3.6
5.7
2.0
Max.
10.0
11.2
11.2
10.7
11.2
100
100
9.1
6.5
-
-
20
20
95
-
-
-
-
-
-
-
Unit
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
ns
ns
3