ADSP-21990BST Analog Devices Inc, ADSP-21990BST Datasheet - Page 33

• Manufacturer Part Number: ADSP-21990BST
• Description: IC DSP CONTROLLER 16BIT 176LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-21990BST

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 20kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP

Serial Port Timing
Table 12
operations, while
Frame Sync operations.
Table 12. Serial Port
1
2
3
4
Parameter
External Clock Timing Requirements
t
t
t
t
t
t
Internal Clock Timing Requirements
t
t
t
t
External or Internal Clock Switching Characteristics
t
t
External Clock Switching Characteristics
t
t
Internal Clock Switching Characteristics
t
t
t
Enable and Three-State Switching Characteristics
t
t
t
t
External Late Frame Sync Switching Characteristics
t
t
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
Word selected timing for I
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DDTE
HDTE
DDTI
HDTI
SCLKIW
DTENE
DDTTE
DTENI
DDTTI
DDTLFSE
DTENLFSE
sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
and
Figure 13
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS Setup Before TCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TFS/RFS Delay After TCLK/RCLK (Internally
Generated FS)
TFS/RFS Hold After TCLK/RCLK (Internally
Generated FS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TCLK/RCLK Width
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from External TCLK
Data Delay from Late External TFS with MCE=1, MFD=0
Data Enable from Late FS or MCE=1, MFD=0
Figure 14
1, 2
2
S mode is the same as TFS/RFS timing (normal framing only).
describe SPORT transmit and receive
and
4
4
Figure 15
4
; RFS Setup Before RCLK
describe SPORT
3
3
4
4
3
3
4
4
5
4
4
3
3
4
4
3
Rev. A | Page 33 of 50 | August 2007
6, 7
3
6, 7
Min
4
4
1.5
4
0.5t
2t
4
3
2
5
3
4
4
0.5t
0
0
3.5
HCLK
HCLK
HCLK
– 1
– 3.5
Max
14
13.4
13.4
0.5t
12.1
13
13
12
10.5
HCLK
+ 2.5
ADSP-21990
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns