ADSP-21990BST Analog Devices Inc, ADSP-21990BST Datasheet - Page 8

• Manufacturer Part Number: ADSP-21990BST
• Description: IC DSP CONTROLLER 16BIT 176LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-21990BST

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 20kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP

ADSP-21990
The SCK line generates the programmed clock pulses for simul-
taneously shifting data out on MOSI and shifting data in on
MISO. In DMA mode only, transfers continue until the SPI
DMA word count transitions from 1 to 0.
In slave mode, the DSP core performs the following sequence to
set up the SPI port to receive data from a master transmitter:
In DMA mode only, reception continues until the SPI DMA
word count transitions from 1 to 0. The DSP core could con-
tinue, by queuing up the next DMA descriptor.
Slave mode transmit operation is similar, except that the DSP
core specifies the data buffer in memory space from which to
transmit data, generates and relinquishes control of the transmit
DMA descriptor, and begins filling the SPI port data buffer. If
the SPI controller is not ready on time to transmit, it can trans-
mit a “zero” word.
DSP SERIAL PORT (SPORT)
The ADSP-21990 incorporates a complete synchronous serial
port (SPORT) for serial and multiprocessor communications.
The SPORT supports the following features:
• Enables and configures the SPI slave port to match the
• Defines and generates a receive DMA descriptor in Page 0
• Enables the SPI DMA engine for a receive access (optional
• Starts receiving the data on the appropriate SCK edges after
• Bidirectional: The SPORT has independent transmit and
• Double buffered: The SPORT section (both receive and
• Clocking: The SPORT can use an external serial clock or
• Word length: Each SPORT section supports serial data
• Framing: Each SPORT section (receive and transmit) can
• Companding in hardware: Each SPORT section can per-
operation parameters set up on the master (data size and
transfer format) SPI transmitter.
of memory space to interrupt at the end of the data transfer
(optional in DMA mode only).
in DMA mode only).
receiving an SPI chip select on the SPISS input pin (recon-
figured programmable flag pin) from a master.
receive sections.
transmit) has a data register for transferring data words to
and from other parts of the processor and a register for
shifting data in or out. The double buffering provides addi-
tional time to service the SPORT.
generate its own in a wide range of frequencies down
to 0 Hz.
word lengths from three to 16 bits that can be transferred
either MSB first or LSB first.
operate with or without frame synchronization signals for
each data-word; with internally generated or externally
generated frame signals; with active high or active low
frame signals; with either of two pulse widths and frame
signal timing.
form A law and μ law companding according to CCITT
recommendation G.711.
Rev. A | Page 8 of 50 | August 2007
ANALOG-TO-DIGITAL CONVERSION SYSTEM
The ADSP-21990 contains a fast, high accuracy, multiple input
analog-to-digital conversion system with simultaneous sam-
pling capabilities. This analog-to-digital conversion system
permits the fast, accurate conversion of analog signals needed in
high performance embedded systems. Key features of the ADC
system are:
The ADC system is based on a pipeline flash converter core, and
contains dual input sample-and-hold amplifiers so that simulta-
neous sampling of two input signals is supported. The ADC
system provides an analog input voltage range of 2.0 V p-p and
provides 14-bit performance with a clock rate of up to
HCLK
• Direct memory access with single cycle overhead: using the
• Interrupts: Each SPORT section (receive and transmit)
• Multichannel capability: The SPORT can receive and trans-
• Each SPORT channel (Tx and Rx) supports a DMA buffer
• The SPORT operates at a frequency of up to one-half the
• The SPORT is capable of UART software emulation.
• 14-bit pipeline (6-stage pipeline) flash analog-to-digital
• 8 dedicated analog inputs.
• Dual-channel simultaneous sampling capability.
• Programmable ADC clock rate to maximum of HCLK 4.
• First channel ADC data valid approximately 375 ns after
• All 8 inputs converted in approximately 725 ns (at
• 2.0 V peak-to-peak input voltage range.
• Multiple convert start sources.
• Internal or external voltage reference.
• Out of range detection.
• DMA capable transfers from ADC to memory.
built-in DMA master, the SPORT can automatically receive
and/or transmit multiple memory buffers of data with an
overhead of only one DSP cycle per data-word. The on-
chip DSP via a linked list of memory space resident DMA
descriptor blocks can configure transfers between the
SPORT and memory space. This chained list can be
dynamically allocated and updated.
generates an interrupt upon completing a data-word trans-
fer, or after transferring an entire buffer or buffers if DMA
is used.
mit data selectively from channels of a serial bit stream that
is time division multiplexed into up to 128 channels. This is
especially useful for T1 interfaces or as a network commu-
nication scheme for multiple processors. The SPORTs also
support T1 and E1 carrier systems.
of up to eight, 16-bit transfers.
clock frequency of the HCLK.
converter.
CONVST (at 20 MSPS).
20 MSPS).
4. The ADC system can be programmed to operate at