XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet - Page 34

• Manufacturer Part Number: XC4005L-5PQ100C
• Description: IC 3.3V FPGA 196 CLB'S 100-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ100C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1121

XC4000 Series Field Programmable Gate Arrays
I/O Routing
XC4000-Series devices have additional routing around the
IOB ring.
VersaRing facilitates pin-swapping and redesign without
affecting board layout. Included are eight double-length
lines spanning two CLBs (four IOBs), and four longlines.
Global lines and Wide Edge Decoder lines are provided.
XC4000EX devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
Figure
only in XC4000EX devices.
4-38
Figure 32: High-Level Routing Diagram of XC4000-Series VersaRing (Left Edge)
WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000EX only)
32. The shaded arrows represent routing present
This routing is called a VersaRing.
Connect
Direct
IOB
IOB
WED
WED
WED
Decode
INTERCONNECT
Edge
Double Long Global
The
Clock
Figure 33
XC4000EX VersaRing. The area shown includes two IOBs.
There are two IOBs per CLB row or column, therefore this
diagram corresponds to the CLB routing diagram shown in
Figure 27 on page
and routing connections present only in XC4000EX
devices.
Octal
is a detailed diagram of the XC4000E and
34. The shaded areas represent routing
September 18, 1996 (Version 1.04)
X5995
Quad
Single
Double
Long
Direct
Connect
Long