XC6VCX75T-1FFG484C Xilinx Inc, XC6VCX75T-1FFG484C Datasheet - Page 31

• Manufacturer Part Number: XC6VCX75T-1FFG484C
• Description: IC FPGA VIRTEX 6 74K 484FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-1FFG484C

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 240
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 41: Output Delay Measurement Methodology (Cont’d)
Input/Output Logic Switching Characteristics
Table 42: ILOGIC Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
HT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVDCI/HSLVDCI, 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
HSTL, Class III, with DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
SSTL, Class I & II, 2.5V, with DCI
Setup/Hold
T
T
T
T
Combinatorial
T
T
Sequential Delays
T
T
T
T
T
Set/Reset
T
ICE1CK
ISRCK
IDOCK
IDOCKD
IDI
IDID
IDLO
IDLOD
ICKQ
RQ_ILOGIC
GSRQ_ILOGIC
RPW_ILOGIC
C
The value given is the differential output voltage.
REF
Symbol
/T
/T
/T
/T
ICKSR
IOCKD
is the capacitance of the probe, nominally 0 pF.
ICKCE1
IOCKDD
Description
CE1 pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY)
D pin to O pin propagation delay, no Delay
DDLY pin to O pin propagation delay (using IODELAY)
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY)
CLK to Q outputs
SR pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR inputs
Description
www.xilinx.com
LDT_25
HSTL_III_DCI_18
LVPECL_25
LVDCI_25, HSLVDCI_25
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
HSTL_III_DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
SSTL2_I_DCI, SSTL2_II_DCI
I/O Standard
Attribute
0.96/–0.10
0.27/0.04
0.10/0.54
0.14/0.42
10.51
0.20
0.25
0.64
0.68
0.71
1.15
1.20
-2
Virtex-6 CXT Family Data Sheet
Speed Grade
R
100
100
()
1M
1M
1M
50
50
50
50
50
50
REF
C
0.96/–0.10
(pF)
REF
0.14/0.40
0.27/0.04
0.10/0.54
0
0
0
0
0
0
0
0
0
0
0
10.51
0.20
0.25
0.64
0.68
0.71
1.15
1.20
(1)
-1
V
V
V
V
V
1.25
0.75
MEAS
(V)
0
0
0.9
0.9
1.1
REF
REF
REF
REF
(2)
(2)
ns, Min
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
0.75
1.25
(V)
0.6
1.5
0.9
1.8
0.9
REF
0
0
0
0
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