XC6VCX75T-2FFG784I Xilinx Inc, XC6VCX75T-2FFG784I Datasheet
XC6VCX75T-2FFG784I
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XC6VCX75T-2FFG784I Summary of contents
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DS153 (v1.6) February 11, 2011 General Description Virtex®-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs block RAM, up ...
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... Virtex-6 CXT FPGA package combinations with the maximum available I/Os per package are shown in Table 2: Virtex-6 CXT FPGA Device-Package Combinations and Maximum Available I/Os FF484 Package FFG484 Size (mm Device GTs XC6VCX75T 8 GTXs XC6VCX130T 8 GTXs XC6VCX195T XC6VCX240T Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). ...
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... Reference these specifications when considering device migration to the Virtex-6 LXT and SXT families. Table 4 gives the specific device ID codes for the Virtex-6 CXT devices. Table 4: Virtex-6 CXT FPGA Device ID Codes Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T www.xilinx.com Virtex-6 CXT Family Data Sheet ...
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... MGTTXN Notes: 1. The XC6VCX75T has 8 GTX I/O channels in the FF484/FFG484 package and 12 GTX I/O channels in the FF784/FFG784 package. 2. The XC6VCX130T has 8 GTX I/O channels in the FF484/FFG484 package, 12 GTX I/O channels in the FF784/FFG784 package, and 16 GTX I/O channels in the FF1156/FFG1156 package. 3. The XC6VCX195T has 12 GTX I/O channels in the FF784/FFG784 package and 16 GTX I/O channels in the FF1156/FFG1156 package. ...
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... Table 8: Available I/O Pin/Device/Package Combinations CXT Virtex-6 Device Available User I/Os XC6VCX75T Differential I/O Pairs Available User I/Os XC6VCX130T Differential I/O Pairs Available User I/Os XC6VCX195T Differential I/O Pairs Available User I/Os XC6VCX240T Differential I/O Pairs GTX Transceivers in CXT Devices CXT devices have between gigabit transceiver circuits. Each GTX transceiver is a combined transmitter and receiver capable of operating at a data rate between 480 Mb/s and 3 ...
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FF484 Package Placement Diagrams Figure 2 and Figure 3 show the placement diagrams for the GTX transceivers in the FF484 package. Note: Unbonded locations in the FF484 package are: • CX75T: X0Y8, X0Y9, X0Y10, X0Y11 • CX130T: X0Y0, X0Y1, X0Y2, ...
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FF784 Package Placement Diagrams Figure 4 through Figure 6 show the placement diagrams for the GTX transceivers in the FF784 package. Note: Unbonded locations in the FF784 package are: • CX130T: X0Y0, X0Y1, X0Y2, X0Y3 • CX195T: X0Y0, X0Y1, X0Y2, ...
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X-Ref Target - Figure 6 AC3 AC4 CX75T: GTXE1_X0Y3 CX130T: GTXE1_X0Y7 CX195T: GTXE1_X0Y7 Y1 CX240T: GTXE1_X0Y7 Y2 AE3 CX75T: GTXE1_X0Y2 AE4 CX130T: GTXE1_X0Y6 CX195T: GTXE1_X0Y6 CX240T: GTXE1_X0Y6 AB1 AB2 W4 W3 QUAD_114 AA4 AA3 AG3 AG4 CX75T: GTXE1_X0Y1 CX130T: GTXE1_X0Y5 ...
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FF1156 Package Placement Diagrams Figure 7 through Figure 10 show the placement diagrams for the GTX transceivers in the FF1156 package. X-Ref Target - Figure CX130T: GTXE1_X0Y15 CX195T: GTXE1_X0Y15 CX240T: GTXE1_X0Y15 CX130T: GTXE1_X0Y14 ...
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X-Ref Target - Figure CX130T: GTXE1_X0Y7 CX195T: GTXE1_X0Y7 CX240T: GTXE1_X0Y7 CX130T: GTXE1_X0Y6 CX195T: GTXE1_X0Y6 CX240T: GTXE1_X0Y6 QUAD_114 CX130T: GTXE1_X0Y5 CX195T: GTXE1_X0Y5 CX240T: GTXE1_X0Y5 V1 V2 ...
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Virtex-6 CXT FPGA Electrical Characteristics Introduction Virtex-6 CXT FPGAs are available in -2 and -1 speed grades, with -2 having the highest performance. Virtex-6 CXT FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the ...
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Table 10: Recommended Operating Conditions Symbol Internal supply voltage relative to GND CCINT Internal supply voltage relative to GND, T Auxiliary supply voltage relative to GND CCAUX Auxiliary supply voltage relative to GND, T Supply voltage ...
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... Table 12. Speed and Temperature Grade Device -2 (C & I) XC6VCX75T 927 XC6VCX130T 1563 XC6VCX195T 2059 XC6VCX240T 2478 XC6VCX75T 1 XC6VCX130T 1 XC6VCX195T 1 XC6VCX240T 2 XC6VCX75T 45 XC6VCX130T 75 XC6VCX195T 113 XC6VCX240T 135 www.xilinx.com Virtex-6 CXT Family Data Sheet ). Xilinx j Units -1 (C & I) 927 mA 1563 mA 2059 mA 2478 mA 1 ...
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... The FPGA must be configured after V Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies. Table 13: Power-On Current for Virtex-6 CXT Devices I CCINTMIN Device Typ XC6VCX75T See I CCINTQ XC6VCX130T See I CCINTQ XC6VCX195T ...
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SelectIO™ DC Input and Output Levels Values for V and V are recommended input voltages. Values for operating conditions at the V and V OL all standards meet their specifications. The selected standards are tested at a ...
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HT DC Specifications (HT_25) Table 16 Specifications Symbol DC Parameter V Supply Voltage CCO V Differential Output Voltage OD V Change in V Magnitude Output Common Mode Voltage OCM V Change in V ...
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LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The V levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant ...
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Table 22: Recommended Operating Conditions for GTX Transceivers Symbol Analog supply voltage for the GTX transmitter and receiver circuits relative MGTAVCC to GND Analog supply voltage for the GTX transmitter and receiver termination MGTAVTT circuits relative to GND Analog supply ...
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GTX Transceiver DC Input and Output Levels Table 25 summarizes the DC output specifications of the GTX transceivers in Virtex-6 CXT FPGAs. Consult the Virtex-6 FPGA GTX Transceivers User Guide for further details. Table 25: GTX Transceiver DC Specifications Symbol ...
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Table 26 summarizes the DC specifications of the clock input of the GTX transceiver. Consult theVirtex-6 FPGA GTX Transceivers User Guide for further details. Table 26: GTX Transceiver Clock DC Input Level Specification Symbol DC Parameter V Differential peak-to-peak input ...
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Table 30: GTX Transceiver User Clock Switching Characteristics Symbol Description F TXOUTCLK maximum frequency TXOUT F RXRECCLK maximum frequency RXREC T RXUSRCLK maximum frequency RX T RXUSRCLK2 maximum frequency RX2 T TXUSRCLK maximum frequency TX T TXUSRCLK2 maximum frequency TX2 ...
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Table 31: GTX Transceiver Transmitter Switching Characteristics (Cont’d) Symbol (2)(3) T Total Jitter J480 D Deterministic Jitter J480 Notes: 1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX transceiver sites. 2. Using PLL_DIVSEL_FB = 2, ...
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Ethernet MAC Switching Characteristics Consult Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information. Table 33: Maximum Ethernet MAC Performance Symbol Description F Client interface maximum frequency TEMACCLIENT F Physical interface maximum frequency TEMACPHY Notes: 1. When not ...
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Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-6 CXT devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines ...
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... Unless otherwise noted, values apply to all Virtex-6 CXT devices. Table 37: Virtex-6 CXT Device/Production Software and Speed Specification Release Speed Grade Designations Device XC6VCX75T ISE 12.2 (with speed file patch) v1.06 XC6VCX130T XC6VCX195T ISE 12.2 (with speed file patch) v1.06 XC6VCX240T Notes: 1 ...
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IOB Pad Input/Output/3-State Switching Characteristics Table 38 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays described as the delay from IOB pad through the IOPI input ...
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Table 38: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Fast LVCMOS18, Fast ...
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Table 38: IOB Switching Characteristics (Cont’d) I/O Standard LVPECL_25 HSTL_I_12 HSTL_I_DCI HSTL_II_DCI HSTL_II_T_DCI HSTL_III_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_II _T_DCI_18 HSTL_III_DCI_18 DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_I DIFF_HSTL_I_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_HSTL_II _T_DCI_18 DIFF_HSTL_II DIFF_HSTL_II_DCI SSTL2_I_DCI SSTL2_II_DCI SSTL2_II_T_DCI SSTL18_I SSTL18_II SSTL18_I_DCI SSTL18_II_DCI SSTL18_II_T_DCI SSTL15_T_DCI SSTL15_DCI DIFF_SSTL2_I ...
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Table 38: IOB Switching Characteristics (Cont’d) I/O Standard DIFF_SSTL18_II_T_DCI DIFF_SSTL15 DIFF_SSTL15_DCI DIFF_SSTL15_T_DCI Table 39: IOB 3-state ON Output Switching Characteristics (T Symbol T T input to Pad high-impedance IOTPHZ I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 40 shows ...
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Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately ...
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Table 41: Output Delay Measurement Methodology (Cont’d) Description HT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI HSTL, Class III, with DCI ...
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Table 43: OLOGIC Switching Characteristics Symbol Setup/Hold T /T D1/D2 pins Setup/Hold with respect to CLK ODCK OCKD T /T OCE pin Setup/Hold with respect to CLK OOCECK OCKOCE pin Setup/Hold with respect to CLK OSRCK OCKSR ...
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Output Serializer/Deserializer Switching Characteristics Table 45: OSERDES Switching Characteristics Symbol Setup/Hold input Setup/Hold with respect to CLKDIV OSDCK_D OSCKD_D ( input Setup/Hold with respect to CLK OSDCK_T OSCKD_T ( input Setup/Hold ...
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Input/Output Delay Switching Characteristics Table 46: Input/Output Delay Switching Characteristics Symbol IDELAYCTRL T Reset to Ready for IDELAYCTRL DLYCCO_RDY F REFCLK frequency IDELAYCTRL_REF IDELAYCTRL_REF_PRECISION REFCLK precision T Minimum Reset pulse width IDELAYCTRL_RPW IODELAY T IODELAY Chain Delay Resolution IDELAYRESOLUTION Pattern ...
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Table 47: CLB Switching Characteristics (Cont’d) Symbol T BX inputs to BMUX output BXB T BX inputs to DMUX output BXD T CX inputs to CMUX output CXB T CX inputs to DMUX output CXD T DX inputs to DMUX ...
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CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 48: CLB Distributed RAM Switching Characteristics Symbol Sequential Delays T Clock to A – B outputs SHCKO T Clock to AMUX – BMUX outputs SHCKO_1 Setup and Hold Times Before/After Clock CLK ...
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Block RAM and FIFO Switching Characteristics Table 50: Block RAM and FIFO Switching Characteristics Symbol Block RAM and FIFO Clock-to-Out Delays (1) T and T Clock CLK to DOUT output (without output register) RCKO_DO RCKO_DO_REG Clock CLK to DOUT output ...
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Table 50: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Maximum Frequency F Block RAM MAX (Write First and No Change modes) Block RAM (Read First mode) Block RAM (SDP mode) F Block RAM Cascade MAX_CASCADE (Write First and No ...
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DSP48E1 Switching Characteristics Table 51: DSP48E1 Switching Characteristics Symbol Setup and Hold Times of Data/Control Pins to the Input Register Clock T DSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG} T DSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG DSPDCK_C_CREG DSPCKD_C_CREG T /T DSPDCK_D_DREG ...
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Table 51: DSP48E1 Switching Characteristics (Cont’d) Symbol Combinatorial Delays from Input Pins to Cascading Output Pins T DSPDO_{A; B}_{ACOUT; BCOUT} T DSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MULT T DSPDO_D_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MULT T DSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT} T DSPDO__{C, CARRYIN}_{PCOUT, CARRYCASCOUT,MULTSIGNOUT} Combinatorial Delays ...
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Table 51: DSP48E1 Switching Characteristics (Cont’d) Symbol Clock to Outs from Input Register Clock to Cascading Output Pins T DSPCKO_{ACOUT; BCOUT}_{AREG; BREG} T DSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_{AREG, BREG}_MULT T DSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_{AREG, BREG} T DSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_DREG_MULT T DSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_CREG ...
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Configuration Switching Characteristics Table 52: Configuration Switching Characteristics Symbol Power-up Timing Characteristics ( (1) T POR T ICCK T PROGRAM Master/Slave Serial Mode Programming Switching T /T DCCK CCKD T /T DSCCK SCCKD T CCO F MCCK F ...
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Table 52: Configuration Switching Characteristics (Cont’d) Symbol BPI Master Flash Mode Programming Switching (2) T BPICCO T /T BPIDCC BPICCD T INITADDR SPI Master Flash Mode Programming Switching T /T SPIDCC SPIDCCD T SPICCM T SPICCFC T /T FSINIT FSINITH ...
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Clock Buffers and Networks Table 53: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol ( pins Setup/Hold BCCCK_CE BCCKC_CE ( pins Setup/Hold BCCCK_S BCCKC_S (2) T BUFGCTRL delay from I0/ BCCKO_O Maximum Frequency ...
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Table 55: Regional Clock Switching Characteristics (BUFR) Symbol T Clock to out delay from BRCKO_O T Clock to out delay from with Divide Bypass attribute set BRCKO_O_BYP T Propagation delay from CLR to O ...
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Table 57: MMCM Specification (Cont’d) Symbol T Static Phase Offset of the MMCM Outputs STATPHAOFFSET T MMCM Output Jitter OUTJITTER T MMCM Output Clock Duty Cycle Precision OUTDUTY T MMCM Maximum Lock Time LOCKMAX F MMCM Maximum Output Frequency OUTMAX ...
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... MMCM output jitter is already included in the timing calculation. DS153 (v1.6) February 11, 2011 Product Specification Description XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Description XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Description XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T www.xilinx.com Virtex-6 CXT Family Data Sheet Speed Grade Device -2 -1 5.88 5.88 6.00 6.00 6 ...
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... Use IBIS to determine any duty-cycle distortion incurred using various standards. DS153 (v1.6) February 11, 2011 Product Specification Description Device XC6VCX75T (2) without MMCM XC6VCX130T XC6VCX195T XC6VCX240T Description (2) with MMCM XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Description (2) XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T www.xilinx.com Virtex-6 CXT Family Data Sheet Speed Grade ...
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... Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS153 (v1.6) February 11, 2011 Product Specification Description (1) (2) XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Description Device (1) XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T www.xilinx.com Virtex-6 CXT Family Data Sheet Speed Grade Device -2 -1 All 0.12 0.12 ...
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Table 66: Sample Window Symbol T Sampling Error at Receiver Pins SAMP T Sampling Error at Receiver Pins using BUFIO SAMP_BUFIO Notes: 1. This parameter indicates the total sampling error of Virtex-6 CXT FPGA DDR input registers, measured across voltage, ...
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... Removed T 06/30/10 1.3 Production release of XC6VCX130T and XC6VCX240T in grade SDR values in Table 07/28/10 1.4 Production release of XC6VCX75T and XC6VCX195T in software with speed file v1.06 using the Speed File Patch. Updated PCI compliance on page 1. Added values to in Table Table 10/14/10 1.5 Moved data sheet to Production status on the first page. Updated speed file with ISE 12.3 software with speed file v1 ...
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