XC6VCX75T-2FFG784I Xilinx Inc, XC6VCX75T-2FFG784I Datasheet - Page 50

• Manufacturer Part Number: XC6VCX75T-2FFG784I
• Description: IC FPGA VIRTEX 6 74K 784FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-2FFG784I

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 66: Sample Window
Table 67: Pin-to-Pin Setup/Hold and Clock-to-Out
Revision History
The following table shows the revision history for this document:
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
T
T
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T
Pin-to-Pin Clock-to-Out Using BUFIO
T
SAMP
SAMP_BUFIO
PSCS
ICKOFCS
07/08/09
02/05/10
This parameter indicates the total sampling error of Virtex-6 CXT FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of Virtex-6 CXT FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Date
Symbol
/T
PHCS
Symbol
Version
Sampling Error at Receiver Pins
Sampling Error at Receiver Pins using BUFIO
1.0
1.1
Setup/Hold of I/O clock
Clock-to-Out of I/O clock
Initial Xilinx release.
Removed Figure 11: Placement Diagram for the FF1156 Package (5 of 5) from page 11 as there are
only 16 GTX transceivers in the FF1156 package. Corrected the placement diagrams in
through
Figure
Description
10.
Description
(1)
www.xilinx.com
(2)
Description of Revisions
Device
All
All
–0.33/1.31
610
400
5.19
-2
-2
Virtex-6 CXT Family Data Sheet
Speed Grade
Speed Grade
–0.33/1.31
610
400
-1
5.19
-1
Figure 2
Units
Units
ps
ps
ns
ns
50