XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 12

• Manufacturer Part Number: XC5VSX50T-2FF665C
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 Family Overview
Virtex-5 FPGA Ordering Information
Virtex-5 FPGA ordering information shown in
X-Ref Target - Figure 1
Revision History
The following table shows the revision history for this document.
12
04/14/06
05/12/06
09/06/06
10/12/06
12/28/06
02/02/07
05/23/07
09/04/07
12/11/07
12/17/07
03/31/08
04/25/08
05/07/08
06/18/08
09/23/08
02/6/09
Date
Example: XC5VLX50T-1FFG665C
Note:
1) -3 speed grade is not available in all devices
Speed Grade
Version
(-1, -2, -3
Device Type
1.0
1.1
2.0
2.1
2.2
3.0
3.1
3.2
3.3
3.4
4.0
4.1
4.2
4.3
4.4
5.0
(1)
)
Initial Xilinx release.
First version posted to the Xilinx website. Minor typographical edits and description updates to highlight
new features. Removed LUT utilization bullet from
Added LXT platform to entire document. This includes descriptions of the RocketIO GTP transceivers,
the Ethernet MACs, and the PCI Express Endpoint block.
Added LX85T devices. Added System Monitor descriptions and functionality.
Added LX220T devices. Revised the Total I/O banks for the LX330 in
XC5VLX50T-FFG665 example in
(Class I and II)," page
Added the SXT platform to entire document.
Removed support for IEEE 1149.6
Revised maximum line rate from 3.2 Gb/s to 3.75 Gb/s in entire document.
Added LX20T, LX155T, and LX155 devices.
Added Disclaimer. Revised CMT section on
Block Plus Wrapper for PCI Express," page
Added FXT platform to entire document.
Clarified information in the following sections:
and
To avoid confusion with PLL functionality, removed PMCD references in
Added XC5VSX240T to entire document.
Updated throughout data sheet that the RocketIO GTX transceivers are designed to run from 150 Mb/s
to 6.5 Gb/s.
Clarified PPC440MC_DDR2 memory controller on
Revised Ethernet MAC column in
(10/100/1000 Mb/s) Ethernet MACs," page
Added TXT platform to entire document.
Revised RocketIO GTX transciever datapath support on
Changed document classification to Product Specification from Advance Product Specification.
"Tri-Mode Ethernet Media Access Controller."
Figure 1: Virtex-5 FPGA Ordering Information
Figure 1
7.
www.xilinx.com
applies to all packages including Pb-Free.
Figure
Table 1, page 2
Temperature Range:
Number of Pins
Pb-Free
Package Type
C = Commercial (T
I = Industrial (T
1. Clarified support for
9.
10.
page
"Integrated Endpoint Block for PCI Express Compliance"
Revision
3. Clarified
and added Note 5. Also updated
"Virtex-5 FPGA Logic," page
page
page
5.
J
= –40°C to +100°C)
J
"Virtex-5 FPGA LogiCORE Endpoint
10.
= 0°C to +85°C)
"Differential SSTL 1.8V and 2.5V
Table
DS100 (v5.0) February 6, 2009
DS100_01_111006
"Global Clocking," page
1. Revised the
Product Specification
3.
"Tri-Mode
8.
R