XC5VLX110-1FFG1153C Xilinx Inc, XC5VLX110-1FFG1153C Datasheet - Page 15

• Manufacturer Part Number: XC5VLX110-1FFG1153C
• Description: IC FPGA VIRTEX-5 110K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX110-1FFG1153C

• Total Ram Bits: 4718592
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 8640
• No. Of Macrocells: 110000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 800
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

X-Ref Target - Figure 2
Table 29
voltage swing.
RocketIO GTP Transceiver User Guide for further details.
Table 29: GTP_DUAL Tile Clock DC Input Specifications
X-Ref Target - Figure 3
X-Ref Target - Figure 4
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Symbol
V
V
+V
–V
MIN
+V
+V
C
–V
V
R
IDIFF
0
EXT
0
0
ISE
IN
= 0V and V
summarizes the DC specifications of the clock input of the GTP_DUAL tile.
Figure 4
P
N
P–N
Differential peak-to-peak input voltage
Single-ended input voltage
Differential input resistance
Required external AC coupling capacitor
MAX
= 1200mV
shows the peak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 FPGA
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
P – N
DC Parameter
Figure 2: Peak-to-Peak Differential Output Voltage
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1)
Conditions
Figure 3
Min
200
100
80
75
shows the single-ended input
Typ
800
400
105
100
2000
1000
Max
130
200
ds202_02_081809
ds202_03_052708
ds202_04_052708
DV
V
V
PPOUT
IDIFF
ISE
Units
mV
mV
nF
Ω
15