XC5VLX110-1FFG1153C Xilinx Inc, XC5VLX110-1FFG1153C Datasheet - Page 44

• Manufacturer Part Number: XC5VLX110-1FFG1153C
• Description: IC FPGA VIRTEX-5 110K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX110-1FFG1153C

• Total Ram Bits: 4718592
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 8640
• No. Of Macrocells: 110000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 800
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input/Output Delay Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
CLB Switching Characteristics
Table 65: CLB Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
IDELAYCTRL
T
F
IDELAYCTRL_REF_PRECISION
T
IODELAY
T
T
T
T
T
T
T
T
T
Combinatorial Delays
T
T
T
T
T
T
T
T
AXA
AXB
AXC
AXD
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYRESOLUTION
IDELAYPAT_JIT
IODELAY_CLK_MAX
IODCCK_CE
IODCK_INC
IODCK_RST
IODDO_T
IODDO_IDATAIN
IODDO_ODATAIN
ILO
ITO
BXB
BXD
Average Tap Delay at 200 MHz = 78 ps.
Units in ps, peak-to-peak per tap, in High Performance mode.
Delay depends on IODELAY tap setting. See
Symbol
/ T
/ T
Symbol
/ T
IODCKC_INC
IODCKC_RST
IODCKC_CE
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
Reset to Ready for IDELAYCTRL
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
IODELAY Chain Delay Resolution
Pattern dependent period jitter in delay chain
for clock pattern
Pattern dependent period jitter in delay chain
for random data pattern (PRBS 23)
Maximum frequency of CLK input to IODELAY
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
TSCONTROL delay to MUXE/MUXF switching
and through IODELAY
Propagation delay through IODELAY
Propagation delay through IODELAY
TRACE
Description
Description
report for actual values.
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
200.00
Note 3
Note 3
Note 3
50.00
–0.06
–0.12
3.00
0.29
0.18
0.02
0.25
±10
300
±5
-3
0
0.08
0.20
0.31
0.67
0.39
0.46
0.31
0.55
0.36
0.45
-3
1/(64 x F
Speed Grade
Speed Grade
200.00
Note 3
Note 3
Note 3
50.00
–0.06
–0.12
3.00
0.34
0.20
0.04
0.28
±10
REF
250
0.09
0.22
0.35
0.77
0.44
0.52
0.36
0.62
0.41
0.51
±5
-2
0
-2
x 1e
6
)
(1)
0.10
0.25
0.40
0.90
0.53
0.61
0.42
0.73
0.48
0.59
-1
200.00
Note 3
Note 3
Note 3
50.00
–0.06
–0.12
3.00
0.42
0.24
0.06
0.33
±10
250
±5
-1
0
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Units
Note 2
Note 2
Units
MHz
MHz
MHz
µs
ns
ps
ns
ns
ns
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