XC2018-70PC68C Xilinx Inc, XC2018-70PC68C Datasheet - Page 21

• Manufacturer Part Number: XC2018-70PC68C
• Description: IC LOGIC CL ARRAY 1800GAT 68PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC68C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 58
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1003

Notes: 1. Peripheral mode timing determined from last control signal of the logical AND of (CS0, CS1, CS2, WRT) to transition to
Peripheral Mode Programming Switching Characteristics
Controls
(CS0, CS1,
CS2, WRT)
2. CCLK and DOUT timing are the same as for slave mode.
3. At power-up, V
active or inactive state.
layed by holding RESET Low until V
non-monotonically rising V
D/P after V
1
(OUTPUT)
DOUT (2)
OUTPUT
CCLK
WRT
CSO
CS1
CS2
CC
DIN
Description
Active (last active
input to first inactive)
Inactive (first inactive
input to last active)
CCLK
DIN setup
DIN hold
has reached 4.0 V (2.5 V for XC2000L).
CC
must rise from 2.0 V to V
2
3 T
CC
CCC
may require a >1- s High level on RESET, followed by a >6- s Low level on RESET and
CC
has reached 4.0 V (2.5 V for XC2000L). A very long V
CC
1 T
min in less than 25 ms. If this is not possible, configuration can be de-
1
2
3
4
5
CA
4 T
Symbol
2-205
T
T
T
T
T
DC
CA
CI
CCC
DC
CD
5 T
3 T
2 T
CD
CCC
CI
50
Min
0.25
0.25
0
CC
rise time of >100 ms, or a
75
Max
X5384
5.0
Units
ns
ns
ns
s
s