XC4020XL-09PQ208C Xilinx Inc, XC4020XL-09PQ208C Datasheet - Page 2

• Manufacturer Part Number: XC4020XL-09PQ208C
• Description: IC FPGA C-TEMP 3.3V 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4020XL-09PQ208C

• Number Of Logic Elements/cells: 1862
• Number Of Labs/clbs: 784
• Total Ram Bits: 25088
• Number Of I /o: 160
• Number Of Gates: 20000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000E Logic Cell Array Family
XC4000E compared to XC4000
Any XC4000E device is a 100% compatible superset of the
The XC4000E devices have the following additional func-
Synchronous RAM
The two RAMs in any CLB can be changed to synchronous
The read operation is not affected by this change to a
Dual-Port RAM
A separate option converts the 16 x 2 RAM in any CLB into
a 16 x 1 dual-port RAM. In this mode, any operation that
writes into the F-RAM, automatically also writes into the G-
RAM, using the F address. The G-address can, therefore,
not be used to write into the G-RAM.
The CLB can thus be used as an asymmetrical dual-port
Each CLB can be configured as function generators either
H-Function Generator
In XC4000E, the H function generator is more versatile. Its
equivalent XC4000 device, not only functionally, but also
electrically, and in pin-out and configuration bitstream.
tions, most of which are invoked through options in the
configuration bitstream:
write operation. In this synchronous mode, the internal
write operation is controlled by the same clock that drives
the flip-flops. The clock polarity is programmable for the
RAM (both F and G function generators together), but is
independent of the chosen flip-flop polarity. Address,
Data, and WE inputs are latched by this rising or falling
clock edge, and a short internal write pulse is generated
right after the clock edge. This self-timed write operation is
thus effectively edge-triggered.
synchronous write.
RAM, with F being the read address for the F-RAM and the
write address for both F- and G-RAM, while G is the read
address for the G-RAM. Note that F and G can still be
independent read addresses, as they are in XC4000. The
two RAMs together have one read/write port using the F
address, and one read-only port using the G address.
asynchronous single-port, synchronous single-port, or
synchronous dual-port.
inputs can come not only from the F and G function
generators but also from up to three control input lines.
The H function generator can be totally or partially inde-
pendent of the other two function generators.
2
IOB Clock Enable
The two flip-flops in each IOB have a common clock enable
Output Drivers
The output pull-up structure can be globally configured to
Input Thresholds
The input thresholds can be globally configured for either
Global Signal Access to Logic
There is additional access from global clocks to the F and
Mode-Pin Pull-Up Resistors
During configuration, the three mode pins, M0, M1, and
For user mode, the three mode inputs can individually be
The PROGRAM input pin has a permanent weak pull-up.
Soft Startup
Like XC3000A, the XC4000E family has “Soft Startup”.
input,which through configuration can be activated indi-
vidually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This makes the IOBs more versatile, and avoids the
need for clock gating.
be either a TTL-like totem-pole (n-channel pull-up transis-
tor, pulling to a voltage one threshold below Vcc, just like
XC4000) or to be CMOS (p-channel pull-up transistor
pulling to Vcc). Also, the configurable pull-up resistor in
XC4000E is a p-channel transistor that pulls to Vcc,
whereas in XC4000 it is an n-channel transistor that pulls
to a voltage one threshold below Vcc.
TTL ( 1.2 V threshold) or CMOS ( 2.5 V threshold ), just like
XC2000 and XC3000 inputs. Note that the two global
adjustments of input threshold and output level are inde-
pendent of each other.
G function generator inputs.
M2, have weak pull-up resistors. For the most popular
configuration mode, Slave Serial, the mode pins can thus
be left unconnected.
configured with or without weak pull-up or pull-down
resistors
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This avoids the potential
ground bounce when all outputs are turned on simulta-
neously. After start-up, the slew rate of the individual
outputs is, as in the XC4000 family, determined by the
individual configuration option.