XC4020XL-09PQ208C Xilinx Inc, XC4020XL-09PQ208C Datasheet - Page 3

• Manufacturer Part Number: XC4020XL-09PQ208C
• Description: IC FPGA C-TEMP 3.3V 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4020XL-09PQ208C

• Number Of Logic Elements/cells: 1862
• Number Of Labs/clbs: 784
• Total Ram Bits: 25088
• Number Of I /o: 160
• Number Of Gates: 20000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

* Timing is based on the XC4005E. For other devices see XACT timing calculator.
** See preceding page
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew rate limited output
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Propagation Delays
Set-up Time (Note 3)
Hold Time (Note 3)
Output
Propagation Delays
Set-up and Hold Times
Clock
Global Set/Reset
Input
Pad to I1, I2
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
same
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock High or Low time
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on
ground bounce, see pages 8-8 through 8-10.
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
*
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
(slew -rate limited)
Speed Grade
3
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
PID
PLI
PDLI
IKRI
IKLI
PICKD
IKPID
OKPOF
OKPOS
OPF
OPS
TSHZ
TSONF
TSONS
OOK
OKO
CH/
RRI
RPO
MRW
PICK
IKPI
T
CL
Min
-4
Max
18.9
Min Max
4.7
8.3
0
3.7
0
4.0
0
-3
11.2
12.4
14.7
2.5
3.6
7.1
2.8
3.0
4.6
5.8
4.2
8.1
7.2
Min Max Units
-2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns