XE8807AMI026TLF Semtech, XE8807AMI026TLF Datasheet - Page 60

IC MCU LOW PWR MTP FLASH 32-TQFP

XE8807AMI026TLF

Manufacturer Part Number
XE8807AMI026TLF
Description
IC MCU LOW PWR MTP FLASH 32-TQFP
Manufacturer
Semtech
Datasheet

Specifications of XE8807AMI026TLF

Applications
Sensing Machine
Core Processor
RISC
Program Memory Type
FLASH (11 kB)
Controller Series
XE8000
Ram Size
512 x 8
Interface
UART, USRT
Number Of I /o
24
Voltage - Supply
2.4 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP, 32-VQFP
For Use With
XE8000MP - PROG BOARD AND PROSTART2 CARD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
XE8807AMI026TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XE8807AMI026TLF
Manufacturer:
IDT
Quantity:
62
Part Number:
XE8807AMI026TLF
Manufacturer:
Semtech
Quantity:
10 000
9.4
The CoolRISC core has 2 different event levels EV0 and EV1 (Figure 9-1).
The setting and clearing of these events can be done in the stat register (see chapter describing the CPU).
The event handler bundles a certain number of event sources and routes them to one of these two events and
provides the possibility to enable/disable each of them individually. The definition of the event sources is given in
the memory mapping chapter.
RegEvn is an 8-bit register containing flags for the event sources. Those flags are set when the event is enabled
(i.e. if the corresponding bit in the registers RegEvnEn is set) and a rising edge is detected on the corresponding
event source.
Once memorized, writing a ‘1’ in the corresponding bit of RegEvn clears an event flag. Writing a ‘0’ does not modify
the flag. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of event service software. RegEvnPriority contains the number
of the highest event set (its value is 0xFF when no event is memorized). RegEvnEvn indicates the priority level of
the current events.
All event sources are sampled by the highest frequency in the system. A CPU event is generated and memorized
when an event becomes high. The 8 event sources are divided into 2 levels of priority: High (4 event sources) and
Low (4 event sources). Those 2 levels of priority are directly mapped to those supported by the CoolRisc (EV0 and
EV1; see CoolRisc documentation for more information).
© Semtech 2006
Detailed description
7
6
5
4
3
2
1
0
7-0
7-2
1
0
pos.
pos.
pos.
RegEvnEn[7]
RegEvnEn[6]
RegEvnEn[5]
RegEvnEn[4]
RegEvnEn[3]
RegEvnEn[2]
RegEvnEn[1]
RegEvnEn[0]
RegEvnPriority
-
EvnHig
EvnLow
RegEvnPriority
RegEvnEvn
RegEvnEn
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
rw
rw
rw
Table 9-4: RegEvnPriority
Table 9-5: RegEvnEvn
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
11111111
nresetglobal
00000
0 nresetglobal
0 nresetglobal
Table 9-3: RegEvnEn
reset
reset
reset
9-3
1= enable event #7
1= enable event #6
1= enable event #5
1= enable event #4
1= enable event #3
1= enable event #2
1= enable event #1
1= enable event #0
code of highest event set
FF if no event present.
unused
one or more high priority event is
set
one or more low priority event is
set
function
function
function
XE8806A/XE8807A
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