CY7C64713-100AXC Cypress Semiconductor Corp, CY7C64713-100AXC Datasheet - Page 21

• Manufacturer Part Number: CY7C64713-100AXC
• Description: IC MCU USB EZ FX1 16KB 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-100AXC

• Program Memory Type: ROMless
• Package / Case: 100-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1679; CY7C64713-100AXC

Table 8. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *F
TQFP
128
109
113
114
115
110
111
112
4
5
6
7
8
9
TQFP
100
87
88
89
90
91
92
93
3
4
5
6
7
8
SSOP
56
8
9
QFN
56
1
2
PE1 or
T1OUT
PE2 or
T2OUT
PE3 or
RXD0OUT
PE4 or
RXD1OUT
PE5 or
INT6
PE6 or
T2EX
PE7 or
GPIFADR8
RDY0 or
SLRD
RDY1 or
SLWR
RDY2
RDY3
RDY4
RDY5
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input
Input
Input
Input
Input
Input
Default
(PE1)
(PE2)
(PE3)
(PE4)
(PE5)
(PE6)
(PE7)
N/A
N/A
N/A
N/A
N/A
N/A
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active HIGH signal from 8051 Timer-counter1. T1OUT
outputs a high level for one CLKOUT clock cycle when Timer1
overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte timer/counter
overflows.
Multiplexed pin whose function is selected by the PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active HIGH output signal from 8051 Timer2. T2OUT is
active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
Multiplexed pin whose function is selected by the PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active HIGH signal from 8051 UART0. If RXD0OUT
is selected and UART0 is in Mode 0, this pin provides the output data
for UART0 only when it is in sync mode. Otherwise it is a 1.
Multiplexed pin whose function is selected by the PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active HIGH output from 8051 UART1. When the
RXD1OUT is selected and UART1 is in Mode 0, this pin provides the
output data for UART1 only when it is in sync mode. In Modes 1, 2, and
3, this pin is HIGH.
Multiplexed pin whose function is selected by the PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The INT6 pin is
edge-sensitive, active HIGH.
Multiplexed pin whose function is selected by the PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active HIGH input signal to the 8051 Timer2. T2EX reloads
timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in
T2CON.
Multiplexed pin whose function is selected by the PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
RDY2 is a GPIF input signal.
RDY3 is a GPIF input signal.
RDY4 is a GPIF input signal.
RDY5 is a GPIF input signal.
Description
CY7C64713
Page 21 of 55
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