Z9025106PSC Zilog, Z9025106PSC Datasheet
Z9025106PSC
Specifications of Z9025106PSC
Related parts for Z9025106PSC
Z9025106PSC Summary of contents
Page 1
... Z90255 ROM and Z90251 OTP 32 KB Television Controller with OSD Product Specification PS001301-0800 ZiLOG W H ORLDWIDE EADQUARTERS Telephone: 408.558.8500 ¥ Fax: 408.558.8300 ¥ www.ZiLOG.com ¥ 910 E. H milton Avenue ¥ Campbell, CA 95008 A ...
Page 2
... Windows is a registered trademark of Microsoft Corporation. Document Disclaimer © 2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ...
Page 3
Table of Contents 1 Overview 1 1.1 Pin Assignment and Descriptions .................................................... 5 1.2 Single-Purpose Pin Descriptions ..................................................... 7 1.3 Multiplexed Pin Descriptions............................................................ 8 2 Memory Description ........................................................................ 10 2.1 Standard Register File ................................................................... 10 2.2 Expanded Register File ................................................................. ...
Page 4
Pulse Width Modulators .................................................................. 68 9.1 PWM Mode Register ...................................................................... 68 9.2 PWM1 through PWM11 ................................................................. 70 9.3 Digital/Analog Conversion with PWM ............................................ 79 10 Analog-to-Digital Converter ............................................................. 80 11 Electrical Characteristics ................................................................. 83 11.1 Absolute Maximum Ratings ............................................................ ...
Page 5
List of Figures 1 Z90255-Based TV System Application ........................................................ 2 2 Z90255 Block Diagram ................................................................................ 3 3 Z90255 and Z90251 Pin Assignments......................................................... 5 4 Code Development Environment ............................................................... 10 5 Register File Map....................................................................................... 12 6 Program Memory Map ............................................................................... 14 ...
Page 6
KB Television Controller with OSD PS001301-0800 vi ...
Page 7
List of Tables 1 Z90255 Production Device Pin Assignment ............................................... 6 2 Single-Purpose Pin Descriptions ................................................................ 7 3 Multiplexed Pin Descriptions....................................................................... 8 4 Register File Map...................................................................................... 13 5 Watch-Dog Timer Mode Register 0Fh: Bank F ......................................... 15 6 Stop Mode ...
Page 8
Master I2C Data Register 0Ah: Bank C (I2C_DATA) ............................... Master I C Bus Interface Commands ....................................................... 56 39 Port configuration Register 00h: Bank F (PCON) ..................................... 57 40 Port 2 Mode Register F6h: P2M ............................................................... 58 ...
Page 9
Z90255 ROM and Z90251 OTP Controller with On-Screen Display 1 Overview The Z90255 and Z90251 are the ROM and OTP versions of a Television Controller with On-Screen Display (OSD) that contains program memory. • ...
Page 10
FM Audio Decoder Television Composite Tuner Video IF Demodulator Deflection SYNC Tuning Control Front Panel Keypad I/R Detector Figure 1 Z90255-Based TV System Application 32 KB Television Controller with OSD Audio R.G.B. R.G.B. Color MUX HSYNC, VSYNC Unit R.G.B. VBLANK ...
Page 11
... Z90255 Block Diagram Note: PWM 6 can be either a 6-bit or 14-bit output. The Z90255 takes full advantage of ZilogÕs Z8 expanded register file space to offer greater flexibility in creating a user-friendly On-Screen Display (OSD). Three basic addressing spaces are available: Program memory, Video RAM (VRAM) and the Register file. The register file is composed of 300 bytes of general-purpose registers, 16 control and status registers, one I/O port register and three reserved registers ...
Page 12
The OSD module supports 10 rows by 24 columns of characters. Each character color can be specified. There are eight foreground colors and eight background colors. When the foreground and background colors are the same, the background is transparent. If ...
Page 13
Pin Assignment and Descriptions Figure 3 shows the pin numbers for production and OTP device format. PORT56/PWM11 PORT55/PWM6 PORT54/PWM5 PORT53/PWM4 PORT52/PWM3 PORT51/PWM2 PORT50/ PWM10 PORT 40 PORT 60/ADC3 PORT61/ADC2 PORT 41/ADC1 PORT 62/ADC0 AGND PORT 42 PORT 43 PORT ...
Page 14
Table 1 Z90255 Production Device Pin Assignment Name Pin Function V +5 Volts CC GND, AGND 0 Volts IRIN Infrared Remote Capture Input PWM11 14-bit Pulse Width Modulator Output 1 PWM10-PWM1 6-Bit Pulse Width Modulator Output P5 (6-0) Bit Programmable ...
Page 15
Single-Purpose Pin Descriptions Table 2 lists the single-purpose pin acronyms, pin names, and descriptions. Table 2 Single-Purpose Pin Descriptions Acronym Pin Name(s) AGND Analog Ground B Blue G Green GND Ground H Horizontal Sync SYNC IRIN IR Capture Input ...
Page 16
Table 2 Single-Purpose Pin Descriptions (Continued) Acronym Pin Name(s) V Video Blank BLANK V Power Supply CC V Vertical Sync SYNC XTAL1, XTAL2 Time-Based Input Output 1.3 Multiplexed Pin Descriptions Table 3 lists the Multiplexed Pin acronyms, pin names, and ...
Page 17
Table 3 Multiplexed Pin Descriptions (Continued) Acronym Pin Name(s) P61/ADC2 Port 6 bit 1 or Analog-to-Digital Converter Channel 2 P41/ADC1 Port 4 bit 1 or Analog-to-Digital Converter Channel 1 P44/PWM7 Port 4 bit 4 or Pulse Width Modulator 7 P45/PWM8 ...
Page 18
... The Z90251 requires ZilogÕs Z90259ZEM Emulator with its proprietary Zilog Developmental Studio (ZDS) software for programming. To view how code is working, the emulator uses a ZOSD board which connects directly to a television screen. Refer to Figure 4. Develop code on PC Figure 4 Code Development Environment ...
Page 19
Expanded Register File The register file has been expanded to provide additional system control registers, additional general purpose registers, and expanded mapping of peripheral devices and I/O ports in the register address area. The lower nibble of the Register ...
Page 20
Register Pointer Working Register Expanded Register Group Pointer Bank Pointer Z8 Register File %FF %F0 %7F %0F %00 Reserved Expanded Register x = undefined Figure 5 Register File Map 32 KB Television ...
Page 21
Table 4 Register File Map BANK 4 BANK 5 Address Description Address Description 00h-0Fh Gen. Pur. Reg. 00h-0Fh Gen. Pur. Reg. 00h-0Fh BANK A Address Description 00h OSD Control Register(OSD_CNTL) 01h Vertical Position Register(VERT_POS) 02h Horizontal Position Register(HOR_POS) 03h Display ...
Page 22
IR IRQ0(High Byte) 0000h IR IRQ0(Low Byte) 0001h HVSYNC IRQ1(High Byte) 0002h HVSYNC IRQ1(Low Byte) 0003h P62 IRQ2(High Byte) 0004h P62 IRQ2(Low Byte) 0005h P63 IRQ3(High Byte) 0006h P63 IRQ3(Low Byte) 0007h T0 IRQ4(High Byte) 0008h T0 IRQ4(Low Byte) 0009h ...
Page 23
Watch-Dog Timer (WDT) The Watch-Dog Timer (WDT) is driven by an internal RC oscillator. Therefore accuracy is dependent on the tolerance of the RC components. Table 5 describes the Watch-Dog Timer Mode register bits. Table 5 Watch-Dog Timer Mode ...
Page 24
Stop-Mode Recovery. After this point, the register cannot be modified by any means, intentional or otherwise. The WDT is permanently enabled after Reset. To ensure that the WDT is set properly, use the following instructions as the first two instructions: ...
Page 25
NOP instruction (opcode = FFh) immediately before the Halt instruction (opcode 7Fh), that is, NOP FF Halt 7F The Halt Mode is exited by interrupts, generated either externally or internally. When the interrupt service routine is completed, the ...
Page 26
Stop-Mode Recovery (SMR) by the WDT increases the Stop Note: Mode standby current (ICC2). This is because the internal RC oscillator is running to support this recovery mode. The Z90255 and Z90251 have Stop-Mode Recovery (SMR) circuitry. Two SMR methods ...
Page 27
Table 6 Stop Mode Recovery (SMR) Register 0Bh: Bank F (SMR) Bit R Reset Note Read W = Write X = Indeterminate Bit/ Bit Field Position Stop flag Stop Recovery level Stop ...
Page 28
External Clock Divide-by-Two (bit 1) Stop-Mode Recovery Source (bits 2, 3, and 4) Figure 7 illustrates Stop Mode Recovers Source/Level Select. Table 7 Stop Mode Recovery Source Bits Operation POR and/or external reset recovery ...
Page 29
Stop Mode Recovery Level Select (bit 6) Cold or Warm Start (bit 7) SMR SMR VDD P63 P27 P62 Stop-Mode Recovery Edge Select (SMR) Figure ...
Page 30
On-Screen Display The On-Screen Display (OSD) module generates and displays a 10 row by 24 columns of 512 characters 18-dots resolution. The color of each character can be specified independently. The televison OSD controller uses H ...
Page 31
Bit/ Field OSD Blank VRAM Mode Sync Polarity Character Size Vertical Retrace Blanking Bit 4, Sync Polarity, provides the polarity of the H and V must have the same polarity (see Figure 8). This feature is designed to SYNC provide ...
Page 32
Vertical Position Register The Vertical Position Register (Table 6) sets the vertical placement of the OSD on the screen. The unit of measure for placement is the number of scan lines from the top of the TV field. Table 9 ...
Page 33
Horizontal Position Register The Horizontal Position Register sets the horizontal start position of the OSD (Table 7). The unit of measure for placement is the number of pixels from the left of the display screen. Table 10 Horizontal Position Register ...
Page 34
The Second Color feature can be used to implement an analog bar for volume control, tuning, etc. The change step for color is half the character size. Refer to Tables 8 and 9. Second Color Control Register The Second Color ...
Page 35
Bit/ Bit Field Position Reserved 7 HV Interrupt Option 6 SYNC Second Color Position 5,4,3,2,1,0 Note: Column increment is 0.5. Offset is 03h. System software requires that the offset be added to the increment for the second color in the ...
Page 36
Row 8 th Row 9th Row (3) 1st Column Figure 9 Second Color Display 5.3 Mesh and Halftone Effect Mesh is a grid-like area that contains an alternating pixel display of OSD and transparent zones. See Figure 10. The ...
Page 37
Picture Screen Field 1 Field 2 OSD Fringing Figure 10 Mesh On General descriptions of the registers used to control the mesh are contained in Tables 13 through 16. Table 13 Mesh Column Start Register 04h: Bank F (MC_St) Bit ...
Page 38
Bit/ Bit Field Position Reserved Mesh Window Start Table 14 Mesh Column End Register 05h: Bank F (MC_End) Bit 7 6 R/W R/W R/W Reset x x Note Read W ...
Page 39
Bit/ Bit Field Position R/W Value V Delay R/W BLANK Foreground Character for 3 Halftone Effect Reserved 2, 1 Mesh Window Row 0 Bits and 4, VBLANK Delay, set the amount of time ...
Page 40
Bit/ Bit Field Position R/W Halftone Effect Output 7 Delay on P20 Mesh Color P20 for 3 Halftoning Software Field Number/ 2 Polarity of Halftone Effect Output Software Mesh 1 Mesh Enable 0 When working with Progressive ...
Page 41
Table 17 BGR Mesh Colors Bit 3,P20 for Halftone, selects mesh or halftone effect. If bit 3 is set to 1, P20 ...
Page 42
Figure 11 Video Fade (Example) This feature is controlled through the FADE_POS1 (Table 18), FADE_POS2 (Table 19), and ROW_SPACE registers (Table 20 Television Controller with OSD PS001301-0800 34 ...
Page 43
Table 18 Fade Position Register 1 05h: Bank A (FADE_POS1) Bit 7 6 R/W R/W R/W Reset 1 1 Note Read W = Write X = Indeterminate Bit/ Field Reserved Row Number of the Screen Bits 3, 2, ...
Page 44
Inter-Row Spacing Inter-Row Spacing can be from horizontal scan line (HL). A setting called Continuous Row Display. A horizontal interrupt is generated at the start of each row. Software must program the ...
Page 45
Character Generation Character generation provides the content of the OSD. The Z90255 supports 14- pixel (horizontal) by 18-pixel (vertical) character display with 512 character sets. Character Cell Resolution Characters are mapped pixel-by-pixel in Character Generation Read-Only Memory (CGROM). Hex ...
Page 46
The Hex Add column is a hexadecimal number that serves as an address for the group of pixels from the starting point of the scan line. Addressing begins at 0000h and ends at 0023h for the first character. There is ...
Page 47
Character Size and Smoothing Effect The Z90255 supports four character sizes: 1X, 2X, double width, and double height. The 2X size duplicates each pixel horizontally and vertically to reach double size. Figure 14 shows a character at 1X, 2X ...
Page 48
Fringing Effect Fringing means surrounding a character with a different color than the foreground and background colors. Refer back to Figure 8. Fringing adds visual appeal to the character presentation. The fringing effect is enabled or disabled in DISP_ATTR: ...
Page 49
Table 22 Display Attribute Register 03h: Bank A (DISP_ATTR) Bit 7 6 R/W R/W R/W Reset 0 0 Note Read W = Write X = Indeterminate Bit/ Bit Field Position R/W Character Display 7 Master 6 Background Enable ...
Page 50
Bit 5, Fringe Enable, sets the fringe effect ON or OFF. Bit 4, Smoothing Effect Enable, sets smoothing ON or OFF, and is available for 2X and double width characters. Bit 3, RGB Polarity, sets color polarity of OSD color ...
Page 51
Table 23 VRAM Structure and Memory Map Character Code Data Bit[11] , Character Color C[2:0] Row0/Column 0 D[11:8] Row0/Column 1 through 22 D[11:8] Row 0/Column 23 D[11:8] Row1/Column 0 D[11:8] Row1/Column 1 through 22 D[11:8] Row 1/Column 23 D[11:8] Row ...
Page 52
Table 23 VRAM Structure and Memory Map (Continued) Character Code Data Bit[11] , Character Color C[2:0] Row 6 D[11:8] Row 7 D[11:8] Row 8 D[11:8] Row 9 D[11:8] Hardware processes the entire 12 bits of data at the same time ...
Page 53
Table 24 Color Palette Selection Bits Color Index, Bit [10:8] Function 000 Selects background/foreground color in row attribute 001 Selects color palette 0 in the color look-up table 010 Selects color palette 1 in the color look-up table 011 Selects ...
Page 54
Red Red Green Green Blue Blue, nb The registers for color palettes 0 through 6 are listed ...
Page 55
Table 28 Color Palette 2 Register 0Bh: Bank A (CLR_P2) Bit 7 6 R/W R/W R/W Reset 1 1 Note Read W = Write X = Indeterminate Bit/ Bit Field Position R/W Reserved 7, 6 Color Palette 2 ...
Page 56
Bit/ Bit Field Position R/W Reserved 7, 6 Color Palette 4 5,4,3,2,1,0 R/W Table 31 Color Palette 5 Register 0Eh: Bank A (CLR_P5) Bit 7 6 R/W R/W R/W Reset 1 1 Note Read W = Write X ...
Page 57
Row Attribute Register The Row Attribute Register (Table 33) is mapped to VRAM, as shown in Table 20. This register controls row background and foreground display. If the Color Index is set to 000h, the display color is read from ...
Page 58
Additional programming time is available with inter-row spacing. VRAM is updated during that time. If the program has too much to display, black lines appear at the top of the screen. The ...
Page 59
When the Palette Mode value is 1, the Color Palette Selection Bits are used, unless they are set to 0s. In that case, the values in the ROW_ATTR register are used. Bit 2, Horizontal Interrupt Enable, disables or ...
Page 60
H and V Requirements SYNC SYNC and V must meet all TV broadcasting specifications. The minimum H SYNC SYNC width of V must conform to the specification in Figure 16. SYNC Field 1 1/2 H Field 2 V must be ...
Page 61
Z90255 I2C Master Interface The Z90255 has a hardware module which supports the I arbitration and MastersÕ arbitration logic is NOT implemented; in other words, the Z90255 is designed for a Single Master application. 2 The I C interface ...
Page 62
Table 35 Master I C Control Register 0Ch: Bank C (I Bit 7 6 R/W R/W R/W Reset x x Note Read W = Write X = Indeterminate Bit/ Bit Field Position Clock Selection 7 Reserved 6 ...
Page 63
Table 36 Master I C Command Register 0Bh: Bank C (I Bit 7 6 R/W R/W R/W Reset x x Note Read W = Write X = Indeterminate Bit/ Bit Field Position Reserved ...
Page 64
Table 38 Master I C Bus Interface Commands Command Description 000 Send a Start bit followed by the address byte specified in the I register, then fetch the acknowledgment bit in I initialize communication. Nine SCLK cycles are generated. ...
Page 65
Input/Output Ports There are 20 input/output (I/O) ports. In addition, seven pulse-width modulators (PWM), PWM1 through PWM6, and PWM11, can be configured as regular output ports. The maximum number of I/O ports available is 27. Please refer to the ...
Page 66
Table 40 Port 2 Mode Register F6h: P2M 7 6 Bit R Reset 1 1 Note Read W = Write X = Indeterminate Bit/ Bit Field Position P27 I/O Definition 7 P26 I/O Definition 6 P25 ...
Page 67
Bit/ Bit Field Position P27 7 P26 6 P25 5 P24 4 P23 3 P22 2 P21 1 P20 0 7.1 Port 4 Pin-Out Selection Register Bits 5,4,3, and 2 control the configuration of multiplexed pins 20, 19, 18, and ...
Page 68
Bit/ Bit Field Position R/W Reserved 7, 6 P47/PWM10 5 P46/PWM9 4 P45/PWM8 3 P44/PWM7 2 Reserved 1, 0 Table 43 Port 4 Data Register 05h: Bank C (PRT4_DTA) Bit 7 6 R/W R/W R/W Reset x x Note: R ...
Page 69
Bit/ Bit Field Position R/W P42 P41 P40 Table 44 Port 4 Direction Control Register 06h: Bank C (PRT4_DRT) Bit 7 6 R/W R/W R/W Reset 1 1 Note ...
Page 70
Port 5 Pin-Out Selection Register Table 45 PWM Mode Register 0Dh: Bank B (P_MODE) Bit 7 R/W R/W Reset 0 Note Read W = Write X = Indeterminate Table 46 Port 5 Data Register 0Ch: Bank B ...
Page 71
Table 47 Port 5 Direction Control Register 0Eh: Bank B (PRT5_DRT) Bit 7 R/W R/W Reset x Note Read W = Write X = Indeterminate Bit/ Field Reserved P56 I/O Definition P55 I/O Definition P54 I/O Definition P53 ...
Page 72
Bit/ Bit Field Position Reserved P63 3 P62 2 P61 1 P60 0 Table 49 Port 6 Direction Control Register 02h: Bank F (PRT6_DRT) Bit 7 6 R/W R/W R/W Reset 1 1 Note ...
Page 73
Bit/ Field P62 I/O definition P61 I/O definition P60 I/O definition 8 Infrared Interface The Z90255 supports the Infrared (IR) Remote Control interface with a minimum of software overhead. Two bytes of data are received through the Infrared (IR) Interface. ...
Page 74
Bit/ Bit Field Position R/W Reserved CAPint_r 2 CAPint_f 1 Tout_CAP 0 During the interrupt service routine, software must read the contents of Timer Control Register 0. Then it checks which bit is set to ...
Page 75
Bit/ Bit Field Position CAP Glitch 3, 2 CAP Speed 1, 0 Bit 6 resets the IR Capture Timer. To stop the timer, set this bit start the timer, set the bit to 0. Bits 5 and ...
Page 76
Table 53 IR Capture Register 1 04h: Bank C (IR_CP1) Bit R/W Reset Note Read W = Write X = Indeterminate Bit/ Field IR Capture Register 1 9 Pulse Width Modulators The Z90255 has 11 Pulse Width Modulator ...
Page 77
Bit/ Bit Field Position 6-bit/14-bit PWM6 7 PWM 11 / P56 6 PWM 6* / P55 5 PWM 5 / P54 4 PWM 4 / P53 3 PWM 3 / P52 2 PWM 2 / P51 1 PWM 1 / ...
Page 78
Bit/ Bit Field Position Reserved 7, 6 P47/ 5 PWM 10 P46/ 4 PWM9 P45/ 3 PWM 8 P44/ 2 PWM 7 Reserved 1, 0 9.2 PWM1 through PWM11 Two data registers (PWM11H and PWM11L) hold the 14-bit PWM11 ratio. ...
Page 79
Figure 18 and Figure 19 illustrate various timing pulses and resultant frequencies for the 6-bit and 14-bit PWMs XTAL/16/64 (A) PWM2 = 00H (B) PWM2 = 01H (C) PWM2 = 03H (D) PWM2 = 20H (E) PWM2 = ...
Page 80
PWM11-0001H Time Slot = 60H (B) PWM11-0002H Time Slot = 60H (C) PWM11-0003H Tme Slot = 70H Time Slot = 50H (D) PWM11-0004H 70H (E) PWM11-0005H (F) PWM11-007FH (G) One of Distribution Pulse XTAL/128 (H) PWM11 = 0080H (I) ...
Page 81
Table 56 PWM 1 Data Register 02h: Bank B (PWM1) Bit 7 6 R/W R/W R/W Reset x x Note Read W = Write X = Indeterminate Bit/ Bit Field Position Reserved 7, 6 PWM 1 Value 5,4,3,2,1,0 ...
Page 82
Bit/ Bit Field Position Reserved 7, 6 PWM 3 Value 5,4,3,2,1,0 Table 59 PWM 4 Data Register 05h:Bank B (PWM4) Bit 7 6 R/W R/W R/W Reset x x Note Read W = Write X = Indeterminate Bit/ ...
Page 83
Table 61 PWM 6 (6-bit)Data Register 07h: Bank B (PWM6) Bit 7 R/W R/W R/W Reset Read W = Write X = Indeterminate Bit/ Bit Field Position Reserved 7, 6 PWM 6 Value 5,4,3,2,1,0 Table 62 ...
Page 84
Bit/ Bit Field Position Reserved 7, 6 PWM 8 Value 5,4,3,2,1,0 Table 64 PWM 9 Data Register 0Ah: Bank B (PWM9) Bit 7 6 R/W R/W R/W Reset x x Note Read W = Write X = Indeterminate ...
Page 85
Table 66 PWM 6 (14-bit) High Data Register 08h: Bank F (PWM6H) Bit 7 6 R/W R/W R/W Reset x x Note Read W = Write X = Indeterminate Bit/ Bit Field Position Reserved 7, 6 PWM 6 ...
Page 86
Bit/ Bit Field Position Reserved 7, 6 PWM 11 Bits 5,4,3,2,1,0 Table 69 PWM 11 Low Data Register 01h: Bank B (PWM11L) Bit 7 6 R/W R/W R/W Reset 0 0 Note Read W = ...
Page 87
Digital/Analog Conversion with PWM The televison OSD controller can generate square waves which have fixed periods but variable duty cycles. If this type of signal passes through an RC integrator, the output voltage proportional to the ...
Page 88
Analog-to-Digital Converter The Z90255 is equipped with a 4-bit flash analog-to-digital converter (ADC) that can be used as either three or four bit configurations. There are four multiplexed analog-input channels. There are two register addresses, one for 3-bit (Table ...
Page 89
Table 70 3-Bit ADC Data Register 00h: Bank C (3ADC_DTA) Bit 7 6 R/W R/W R/W Reset x 0 Note Read W = Write X = Indeterminate Bit/Field Reserved ADC Speed ADC Input Selection ADC Data Table 71 ...
Page 90
ADC Block Diagram ADC Data Decoder Register ADC Control Figure 21 ADC Block Diagram 32 KB Television Controller with OSD V CC Comparators GND 82 Analog Multiplexer ADC0 ADC1 ADC2 ADC3 PS001301-0800 ...
Page 91
Electrical Characteristics 11.1 Absolute Maximum Ratings Stress exceeding the levels listed in the Operational Limits can cause permanent damage to the device. These limits represent stress limits only, not optimal operating levels. Exposure to maximum rating conditions for extended ...
Page 92
DC Characteristics Table 73 DC Characteristics Symbol Parameter V Power Supply Voltage CC V Input Voltage High IH V Input Voltage Low IL V Input XTAL/Oscillator In High IHC V Input XTAL/Oscillator In Low ILC 1 V Output Voltage ...
Page 93
AC Characteristics The numbers in Table 74 correspond to the numbered signal segments in Figure 22. Table 74 AC Characteristics No. Symbol 1 TpC Hsync L ...
Page 94
Timing Diagram 1 XTAL1 Internal/Reset External/Reset H SYNC OSDX2 Figure 22 Timing Requirements of External Inputs 32 KB Television Controller with OSD 3 7 Hsync IRQn ...
Page 95
Packaging Figure 23 42-Lead Shrink Dual-in-line Package (SDIP) Table 75 Package Dimensions Symbol Television Controller with OSD ...
Page 96
... Ordering Information Part PSI Z90251 Z9025106PSC Z90255 Z9025506PSC Rxxxx* Z9025900ZEM Z9025900ZEM Z9020900TSC Z9020900TSC Note: * xxxx is a unique ROM number assigned to each customer code ROM Code Submission ROM Code Submission Instructions ROM Code can be submitted on ZiLOGÕs web site at http://www.zilog.com. Top Mark Information Mark Permanency: 3X soak into Alpha 2110 for 30 seconds duration each soak ...
Page 97
... Customer Feedback Form Z90255 Product Specification I f there are any problems while operating this product, or any inaccuracies in the specification, please copy and complete this form, then mail or fax it to ZiLOG. Suggestions welcome! Customer Information Name Company Address City/State/Zip Product Information Serial # or Board Fab #/Rev. # ...