Z9025106PSG Zilog, Z9025106PSG Datasheet - Page 23

• Manufacturer Part Number: Z9025106PSG
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSG

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
Watch-Dog Timer (WDT)
The Watch-Dog Timer (WDT) is driven by an internal RC oscillator. Therefore
accuracy is dependent on the tolerance of the RC components. Table 5 describes
the Watch-Dog Timer Mode register bits.
Table 5
WDT During Halt Mode (T2)
Bit 2 determines if the WDT is active during Halt Mode. A 1 value indicates active
during Halt. The default is 1. A WDT timeout during Halt Mode resets control
registers and ports to their default reset conditions.
Bit 3 determines if the WDT is active during Stop mode. A 1 value indicates
active during Stop mode. A WDT timeout during Stop mode resets control
registers and ports to their default reset conditions.
Bits 4, 5, 6 and 7 are reserved and must be cleared to 0.
The WDTMR register is accessible only during the first 60 processor cycles from
the execution of the first instruction after Power-On Reset, Watch-Dog Reset, or a
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Bit/
Field
reserved
WDT During Stop
WDT During Halt
WDT TAP
Watch-Dog Timer Mode Register 0Fh: Bank F
W
7
0
W
6
0
Bit
Position
7-4
3
2
1, 0
W
5
0
R/W
W
W
W
W
32 KB Television Controller with OSD
W
4
0
Value Description
00
01
10
11
0
0
1
0
1
W
3
0
Must be 0
Off
On POR
Off
On POR
12 msec POR
24 msec
96 msec
6 msec
W
2
1
W
1
0
PS001301-0800
W
0
1
15