CY7C65113A-SXC Cypress Semiconductor Corp, CY7C65113A-SXC Datasheet
CY7C65113A-SXC
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CY7C65113A-SXC Summary of contents
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... CMOS outputs Maskable interrupts on all I/O pins ❐ 12-bit free-running timer with one microsecond clock ticks ■ Cypress Semiconductor Corporation Document #: 38-08002 Rev. *E USB Hub with Microcontroller Watchdog timer (WDT) ■ Internal Power-on Reset (POR) ■ ...
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Functional Overview The CY7C65113C device is a one-time programmable 8-bit microcontroller with a built-in 12-Mbps USB hub that supports up to four downstream ports. The microcontroller instruction set has been optimized specifically for USB operations, although the microcontrollers can be ...
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Logic Block Diagram 6-MHz crystal PLL 48 MHz Clock 12-MHz Divider 8-bit CPU 12 MHz PROM 8 KB RAM 256 byte 6 MHz 12-bit Timer Watchdog Timer Power-on Reset Document #: 38-08002 Rev. *E USB Transceiver Repeater USB SIE Interrupt ...
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Contents Pin Configurations ........................................................... 5 Product Summary Tables ................................................ 5 Pin Assignments ......................................................... 5 I/O Register Summary ................................................. 6 Instruction Set Summary ............................................. 7 Programming Model ......................................................... 8 14-bit Program Counter ............................................... 8 8-bit Accumulator (A) ................................................. 10 8-bit Temporary ...
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Pin Configurations Product Summary Tables Pin Assignments Table 1. Pin Assignments Name I/O 28-pin D+[0], D–[0] I D+[1], D–[1] I D+[2], D–[2] I D+[3], D–[3] I/O 23, 24 D+[4], D–[4] I/O 21 ...
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I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the ...
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Table 2. I/O Register Summary (continued) Register Name I/O Address Hub Port Speed 0x4A Hub Port Control (Ports [4:1]) 0x4B Hub Port Suspend 0x4D Hub Port Resume Status 0x4E Hub Ports SE0 Status 0x4F Hub Ports Data 0x50 Hub Downstream ...
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Table 3. Instruction Set Summary (continued) MNEMONIC operand opcode MOV X,expr data 1C MOV X,[expr] direct 1D reserved 1E XPAGE 1F MOV A,X 40 MOV X,A 41 MOV PSP,A 60 CALL addr 50-5F JMP addr 80-8F CALL addr 90-9F JZ ...
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Program Memory Organization Figure 2. Program Memory Space with Interrupt Vector Table after reset 14-bit PC Note that the upper 32 bytes of the 8K PROM are reserved. Therefore, user’s program must not overwrite this space. Document #: 38-08002 Rev. ...
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Accumulator (A) The accumulator is the general-purpose register for the micro- controller. 8-bit Temporary Register (X) The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the ...
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Data Stack Pointer (DSP) The Data Stack Pointer (DSP) supports PUSH and POP instruc- tions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the ...
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The XTALIN and XTALOUT are the clock pins to the microcon- troller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as ...
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Watchdog Reset The WDR occurs when the internal Watchdog Timer rolls over. Writing any value to the write-only Watchdog Reset Clear Register (Figure ) clears the timer. The timer rolls over and WDR occurs not cleared within ...
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General-purpose I/O Ports GPIO CFG OE Internal Data Bus Port Write Port Read Reg_Bit STRB (Latch is Transparent) Interrupt Enable Interrupt Controller There are 11 GPIO pins (P0[7:0] and P1[2:0]) for the hardware interface. Each port can be configured as ...
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A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data Registers. During reset, all of the GPIO pins are set to a high-impedance input state. ...
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Table 4. GPIO Port Output Control Truth Table and Interrupt Polarity Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit Q1, Q2, and Q3 discussed ...
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Free-Running Timer The 12-bit timer operates with a 1-μs tick, provides two interrupts (128 μs and 1.024 ms) and allows the firmware to directly time events that are duration. The lower eight bits of ...
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I C Configuration Register Internal hardware supports communication with external devices through an I [3] 2 discussed in detail in Section . The I C Position bit (Bit 7, Figure 14) and I the SCL (clock) and SDA (data) ...
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Bits [7..0 Data 2 Contains the 8-bit data on the I C Bus Status and Control Bit # 7 6 Bit Name MSTR Mode Continue/Bu sy Read/Write R/W R/W Reset The ...
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Bit 4 : ACK This bit is set or cleared by firmware during receive oper- ation to indicate if the hardware should generate an ACK 2 signal ...
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D+ line and the D– line are LOW at the same time. Bit 6: Watchdog Reset The Watchdog Reset is set during a reset initiated by the Watchdog Timer. This indicates ...
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Bit 0: EPA0 Interrupt Enable 1 = Enable Interrupt on data activity through endpoint A0 Disable Interrupt on data activity through endpoint A0 Bit 1: EPA1 Interrupt Enable 1 = Enable Interrupt on data activity through endpoint A1; ...
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Interrupt Vectors The Interrupt Vectors supported by the USB Controller are listed in has the highest priority, and the highest-numbered interrupt (I Figure 20. Interrupt Controller Function Diagram CLR Enable [0] (Reg 0x20) USB Reset Int CLK ...
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Interrupt Latency Interrupt latency can be calculated from the following equation: Interrupt latency = (Number of clock cycles remaining in the current instruction clock cycles for the JMP instruction) For example 5-clock cycle instruction such as ...
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Port Configuration Register M U GPIO X Pin Port Interrupt 1 = Enable Enable Register 0 = Disable IRA Refer to Sections and for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts. If one port ...
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USB Overview The USB hardware includes a USB Hub repeater with one upstream and up to seven downstream ports. The USB Hub repeater interfaces to the microcontroller through a full-speed serial interface engine (SIE). An external series resistor of R ...
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Connects are recorded by the time a non-SE0 state lasts for more than 2.5 μ downstream port. When a USB device is disconnected from the Hub, the downstream signal pair eventually floats to a single-ended zero . Hub ...
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Bit [0..3] : Port x Enable (where x = 1..4) Set Port x is enabled; Set Port x is disabled Bit [4..7] : Reserved. Set to 0. The Hub Ports Enable register is cleared ...
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The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 27) and the Hub Ports Data Register (Figure 28). The data read from the Hub Ports Data Register is the differential data only ...
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Hub Ports Suspend Bit # 7 6 Bit Name Device Reserved Remote Wakeup Read/Write R/W R/W Reset 0 0 Bit [0..3] : Port x Selective Suspend (where x = 1..4). Set Port x is Selectively Suspended; Set ...
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USB Status and Control Bit # 7 6 Bit Name Endpoint Endpoint Size Mode Read/Write R/W R/W Reset 0 0 Bits[2..0]: Control Action Set to control action as per Table 9. The three control bits allow the upstream port to ...
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Bits[6..0]: Device Address. Firmware writes this bits during the USB enumeration pro- cess to the non-zero address assigned by the USB host. Bit 7: Device Address Enable. Must be set by firmware before the SIE can respond to USB traffic ...
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SETUP token. Any write to this bit by the CPU will clear it (set it to 0). The bit is forced HIGH from the start of ...
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Bits[5..0]: Byte Count. These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are ...
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USB Mode Tables Table 11. USB Register Mode Encoding Mode Moder SETUP Bits Disable 0000 ignore Nak In/Out 0001 accept Status Out Only 0010 accept Stall In/Out 0011 accept Ignore In/Out 0100 accept Isochronous Out 0101 ignore Status In Only ...
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Firmware normally enables the endpoint mode after a SetConfiguration request. Any SETUP packet to an enabled endpoint with mode set to accept SETUPs will be changed by the SIE to 0001 (NAKing INs ...
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Table 13. Details of Modes for Differing Traffic Conditions (see SETUP (if accepting SETUPs) Properties of Incoming Packet Mode Bits token count buffer dval See Table 11 Setup <= 10 data valid See Table 11 Setup > 10 junk ...
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Table 13. Details of Modes for Differing Traffic Conditions (see Out 2 UC valid Out 2 UC valid Out !=2 UC valid Out > ...
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Register Summary Address Register Name Bit 7 0x00 Port 0 Data P0.7 0x01 Port 1 Data P1.7 0x02 Port 2 Data P2.7 0x03 Port 3 Data P3.7 0x04 Port 0 Interrupt Enable P0.7 Intr Enable 0x05 Port 1 Interrupt Enable ...
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Register Summary (continued) Address Register Name Bit 7 0x48 Hub Port Connect Status Reserved 0x49 Hub Port Enable Reserved 0x4A Hub Port Speed Reserved 0x4B Hub Port Control (Ports Port 4 4:1) Control Bit 1 0x4D Hub Port Suspend Device ...
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Sample Schematic 3.3V Regulator IN 2.2 μF Vref 1. UUP USB-B Vbus Vbus 22x2(R D– ext D+ GND SHELL 4.7 nF Optional 250 VAC 10M 6.000 MHz Absolute Maximum Ratings Storage Temperature ................................. –65°C to +150°C Ambient Temperature ...
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Electrical Characteristics MHz; Operating Temperature = 0 to 70°C, V OSC Parameter Description V Reference Voltage REF V Programming Voltage (disabled Operating Current Supply Current—Suspend Mode SB1 I V Operating Current ...
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Switching Characteristics (f Parameter f Clock Rate OSC t Clock Period cyc t Clock HIGH time CH t Clock LOW time CL t Transition Rise Time rfs t Transition Fall Time ffs t Rise/Fall Time Matching; (t rfmfs t Full ...
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Ordering Information Ordering Code PROM Size CY7C65113C-SXC 8 KB CY7C65113C-SXCT 8 KB Package Diagram Document #: 38-08002 Rev. *E Package Type 28-pin SOIC 28-pin SOIC-Tape and Reel Figure 36. 28-Pin (300-Mil) Molded SOIC CY7C65113C Operating Range Commercial Commercial 51-85026 *E ...
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Document History Page Document Title: CY7C65113C USB Hub with Microcontroller Document Number: 38-08002 Orig. of REV. ECN NO. Issue Date Change ** 109965 02/22/02 *A 120372 12/17/02 *B 124522 03/13/03 *C 368601 See ECN *D 429098 See ECN *E 3057657 ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...