CY7C65113A-SXC Cypress Semiconductor Corp, CY7C65113A-SXC Datasheet - Page 15

• Manufacturer Part Number: CY7C65113A-SXC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113A-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Voltage - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-1647

A read from a GPIO port always returns the present state of the
voltage at the pin, independent of the settings in the Port Data
Registers. During reset, all of the GPIO pins are set to a
high-impedance input state. Writing a ‘0’ to a GPIO pin drives the
pin LOW. In this state, a ‘0’ is always read on that GPIO pin
unless an external source overdrives the internal pull-down
device.
As shown in
represents a rising edge interrupt (LOW to HIGH), and a negative
polarity on an input pin represents a falling edge interrupt (HIGH
to LOW).
The GPIO interrupt is generated when all of the following condi-
tions are met: the Interrupt Enable bit of the associated Port
Interrupt Enable Register is enabled, the GPIO Interrupt Enable
bit of the Global Interrupt Enable Register (Figure 18) is enabled,
the Interrupt Enable Sense (bit 2, Figure 17) is set, and the GPIO
pin of the port sees an event matching the interrupt polarity.
Document #: 38-08002 Rev. *E
GPIO Configuration
Bit #
Bit Name
Read/Write
Reset
Table 4
Reserved
below, a positive polarity on an input pin
7
-
-
Reserved
6
-
-
Figure 8. GPIO Configuration Register.
Reserved
5
-
-
Reserved
4
-
-
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal
pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not
driven internally). In addition, the interrupt polarity for each port
can be programmed. The Port Configuration bits
the Interrupt Enable bit
the interrupt polarity of the port pins
The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register (Figure 6 through
by its associated Port Configuration bits as shown in the GPIO
Configuration Register (Figure ). These ports are configured on
a per-port basis, so all pins in a given port are configured
together. The possible port configurations are detailed in
As shown in this table below, when a GPIO port is configured with
CMOS outputs, interrupts from that port are disabled.
During reset, all of the bits in the GPIO Configuration Register
are written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.
Config Bit 1
Port 1
R/W
3
0
Config Bit 0
(Figure 10
Port 1
R/W
2
0
through
Config Bit 1
Port 0
R/W
1
0
CY7C65113C
Figure
Address 0x08
Config Bit 0
(Figure
10) determine
Page 15 of 46
Figure
Port 0
R/W
0
0
Table
) and
) and
4.
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