CY7C65113A-SXC Cypress Semiconductor Corp, CY7C65113A-SXC Datasheet - Page 13

• Manufacturer Part Number: CY7C65113A-SXC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113A-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Voltage - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-1647

chdog Timer
ster
write to
Watchdog Reset
The WDR occurs when the internal Watchdog Timer rolls over.
Writing any value to the write-only Watchdog Reset Clear
Register (Figure ) clears the timer. The timer rolls over and WDR
occurs if it is not cleared within t
Section for the value of t
and Control Register (Figure 17) is set to record this event (the
register contents are set to 010X0001 by the WDR). A Watchdog
Timer Reset lasts for 2 ms, after which the microcontroller begins
execution at ROM address 0x0000.
Figure 4. Watchdog Reset (Address 0x26)
The USB transmitter is disabled by a Watchdog Reset because
the USB Device Address Registers are cleared (see Section ).
Otherwise, the USB Controller would respond to all address 0
transactions.
It is possible for the WDR bit of the Processor Status and Control
Register (Figure 17) to be set following a POR event. If a
firmware interrogates the Processor Status and Control Register
for a set condition on the WDR bit, the WDR bit should be ignored
if the POR bit is set (Bit 3 of the Processor Status and Control
Register).
Document #: 38-08002 Rev. *E
t
WATCH
No write to WDT
register, so WDR
goes HIGH
WATCH
). Bit 6 of the Processor Status
WATCH
2 ms
of the last clear (see
Execution begin
Reset Vector 0x
Suspend Mode
The CY7C65113C can be placed into a low-power state by
setting the Suspend bit of the Processor Status and Control
register. All logic blocks in the device are turned off except the
GPIO interrupt logic and the USB receiver. The clock oscillator
and PLL, as well as the free-running and Watchdog timers, are
shut down. Only the occurrence of an enabled GPIO interrupt or
non-idle bus activity at a USB upstream or downstream port
wakes the part out of suspend. The Run bit in the Processor
Status and Control Register must be set to resume a part out of
suspend.
The clock oscillator restarts immediately after exiting suspend
mode. The microcontroller returns to a fully functional state 1 ms
after the oscillator is stable. The microcontroller executes the
instruction following the I/O write that placed the device into
suspend mode before servicing any interrupt requests.
The GPIO interrupt allows the controller to wake-up periodically
and poll system components while maintaining a very low
average power consumption. To achieve the lowest possible
current during suspend mode, all I/O should be held at V
Gnd. Note: This also applies to internal port pins that may not be
bonded in a particular package.
Typical code for entering suspend is shown below:
pins)
wake-up
suspend, wait for USB activity (or GPIO Interrupt)
...
...
mov a, 09h
iowr FFh
nop
...
; All GPIO set to low-power state (no floating
; Enable GPIO interrupts if desired for
; Set suspend and run bits
; Write to Status and Control Register – Enter
; This executes before any ISR
; Remaining code for exiting suspend routine.
CY7C65113C
Page 13 of 46
CC
or
[+] Feedback