Z8S18033VEC Zilog, Z8S18033VEC Datasheet - Page 20

• Manufacturer Part Number: Z8S18033VEC
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog

Specifications of Z8S18033VEC

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3115

Low. I/O operations continue as before the
The Z8S180/Z8L180 leaves
bit (ICR5) and bits 3 and 6 of the CPU Control Register
(CCR3, CCR6) all zero and executing the
The oscillator and
blocked from the CPU core and DMA channels to reduce
power consumption. DRAM refresh stops, but interrupts
and granting to an external Master can occur. Except when
the bus is granted to an external Master, A19–0 and all con-
trol signals except
except for the DMA channels.
The Z8S180/Z8L180 leaves
Low on
Low on
Interrupt from an enabled on-chip source
External request on
Enabled external request on
INT , NMI
A –A
MREQ
i
HALT
19
PHI
M1
RD
This mode is entered by keeping the
, an interrupt request from an on-chip source,
0
Note:
HALT Opcode Fetch Cycle
HALT Opcode Address
T
2
output continue operating, but are
are maintained High.
indicates an indefinite delay.
T
mode in response to:
3
mode in response to a
,
, or
instruction.
instruction,
is
In case of an interrupt, the return address is the instruction
following the
branch back to the
terrupt or can examine the new state of the system/applica-
tion and respond appropriately.
an external request on
If an interrupt source is individually disabled, it cannot bring
the Z8S180/Z8L180 out of
source is individually enabled, and the
interrupts are globally enabled (by an EI instruction), the
highest priority active interrupt occurs with the return ad-
dress being the instruction after the
interrupt source is individually enabled, but the
so that interrupts are globally disabled (by a DI instruction),
the Z8S180/Z8L180 leaves
ing the following instruction(s).
HALT Mode
HALT Opcode Address + 1
, or
.
instruction. The program can either
instruction to wait for another in-
, or an external request on
T
1
Interrupt
Acknowledge Cycle
mode by simply execut-
mode. If an interrupt
instruction. If an
T
2
bit is
1
ZiLOG
bit is
so that
0
,