Z8018220AEG Zilog, Z8018220AEG Datasheet - Page 8

• Manufacturer Part Number: Z8018220AEG
• Description: IC 20MHZ STATIC MIMIC 100-VQFP
• Manufacturer: Zilog

Specifications of Z8018220AEG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4693; Z8018220AEG

Zilog
Z85230 ESCC SIGNALS (Continued)
/SYNCA, /SYNCB. Synchronization (inputs/outputs, active
Low). These pins can act as either inputs, outputs, or as
part of the crystal oscillator circuit. In the Asynchronous
Receive mode (crystal oscillator option not selected),
these pins are inputs similar to /CTS and /DCD. In this
mode, transitions on these lines affect the state of the Sync
/Hunt status bits in Read Register 0, but have no other
function. /SYNCA is also multiplexed with PC4 (parallel
Port C, bit 4) on the /SYNCA/PC4 pin.
In External Synchronization mode with the crystal oscillator
not selected, these lines also act as inputs. In this mode
/SYNC must be driven Low two receive clock cycles after
the last bit in the sync character is received. Character
assembly begins on the rising edge of the receive clock
immediately preceding the activation of /SYNC.
In the Internal Synchronization mode, (Monosync and
Bisync) with the crystal oscillator not selected, these pins
act as outputs and are active only during the part of the
receive clock cycle in which sync characters are
recognized. The sync condition is not latched, so these
outputs are active each time a sync character is recognized
(regardless of the character boundaries). In SDLC mode,
these pins act as outputs and are valid on receipt of a flag.
In Z80182/Z8L182 mode 1 the /SYNCB signal is multiplexed
with the 16550 MIMIC interface /HCS input on the /SYNCB
//HCS pin.
/CTSA. Clear To Send (input, active Low). If this pin is
programmed as auto enable, a Low on this input enables
the channel A transmitter. If not programmed as auto
enable, it may be used as a general-purpose input. The
input is Schmitt-trigger buffered to accommodate slow
rise-time input. The ESCC
and can interrupt the Z180
transitions. /CTSA is multiplexed with PC1 (parallel Port C,
bit 1) on the /CTSA/PC1 pin.
/CTSB. Clear To Send (input, active Low). This pin is
similar to /CTSA’s functionality but is applicable to the
channel B transmitter. In Z80182/Z8L182 mode, the /CTSB
signal is multiplexed with the 16550 MIMIC interface /HWR
input on the /CTSB //HWR pin.
/DCDA. Data Carrier Detect (input, active Low). This pin
functions as receiver enables if it is programmed as an
auto enable bit; otherwise, it may be used as a general-
purpose input pin. The pin is Schmitt-trigger buffered to
accommodate slow rise-time signals. The ESCC detects
transitions on this pin and can interrupt the Z180 MPU on
either logic level transitions. /DCDA is also multiplexed
with PC0 (parallel Port C, bit 0) on the /DCDA/PC0 pin.
3-8
™
detects transitions on this input
™
MPU on either logic level
P R E L I M I N A R Y
PS009801-0301
/DCDB. Data Carrier Detect (input, active Low). This pin’s
functionality is similar to /DCDA but applicable to the
channel B receiver. In Z80182/Z8L182 mode 1, /DCDB is
multiplexed with the 16550 MIMIC interface /HRD input on
the /DCDB//HRD pin.
/RTSA. Request to Send (output, active Low). When the
Request to Send (RTS) bit in Write Register 5 channel A is
set, the /RTSA signal goes Low. When the RTS bit is reset
in the Asynchronous mode and auto enables is on, the
signal goes High after the transmitter is empty. In
Synchronous mode or in Asynchronous mode with auto
enables off, the /RTSA pin strictly follows the state of the
RTS bit. The pin can be used as general-purpose output.
/RTSA is multiplexed with PC2 (parallel Port C bit 2). This
/RTSA or PC2 combination is pin multiplexed with /MWR
(active when both the internal /MREQ and /WR are active)
on the /MWR/PC2//RTSA pin. The default function of this
pin on power-up is /MWR which may be changed by
programming bit 3 in the Interrupt Edge/Pin MUX Register
(xxDFH).
/RTSB. Request to Send (output, active Low). This pin is
similar in functionality as /RTSA but is applicable on
channel B. The /RTSB signal is multiplexed with the Z180
MPU /TEND1 signal and the 16550 MIMIC interface
/HRxRDY signal on the /TEND1//RTSB//HRxRDY pin.
/DTR//REQA. Data Terminal Ready (output, active Low).
This pin functions as it is programmed into the DTR bit. It
can also be used as general-purpose output (transmit) or
as request lines for the DMA controller. The ESCC allows
full duplex DMA transfers. /DTR//REQA is also multiplexed
with PC3 (parallel Port C, bit 3) on the /DTR//REQA
/PC3 pin.
/DTR//REQB. Data Terminal Ready (output, active Low).
This pin functions as it is programmed into the DTR bit. It
can also be used as general-purpose output (transmit) or
as request lines for the DMA controller. The ESCC allows
full duplex DMA transfers. The /DTR//REQB signal is
multiplexed with the Z180 MPU TxS signal and the 16550
MIMIC interface HINTR signal on the /TxS//DTR//REQB
//HINTR pin.
/W//REQA. Wait/Request (output, open drain when
programmed for the Wait function, driven High or Low
when programmed for a Request function). This dual-
purpose output can be programmed as Request (receive)
lines for a DMA controller or as Wait lines to synchronize
the Z180 MPU to the ESCC data rate. The reset state is
Wait. The ESCC allows full duplex DMA transfers.
/W//REQA is also multiplexed with PC5 (parallel Port C, bit
5) on the /W//REQA/PC5 pin.
Z
ILOG
I
NTELLIGENT
DS971820600
Z80182/Z8L182
P
ERIPHERAL