Z8S18010FSC00TR Zilog, Z8S18010FSC00TR Datasheet - Page 57

• Manufacturer Part Number: Z8S18010FSC00TR
• Description: IC Z180 MPU 80QFP
• Manufacturer: Zilog

Specifications of Z8S18010FSC00TR

• Processor Type: Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

ZiLOG
The DMA I/O Address Register specifies the I/O device for
channel 1 transfers. This address may be a destination or
source I/O device.
bits. The most significant byte identifies the Request Hand-
shake signal and controls the Alternating Channel feature.
and
each contain 8 address
channels are programmed for the same I/O source or I/O
destination. In this case, a
= 0) on channel 0 sets bit 6 (
enables the channel 1 request and blocks the channel 0
request. Similarly, a channel end condition on channel 1
clears bit 6 (
and blocks the channel 1 request. For external requests, the
request from the device must be routed or connected to both
the
7 (
by bits
nel 0 request operates normally. When
is
not presented to channel 0; however, the channel 1 request
operates normally. The
to select which channel should operate first; however, this
operation should be executed only when both channels are
stopped (both
an I/O source, the following bits select which source hand-
shake signal should control the transfer:
If
bits select which destination handshake signal should con-
trol the transfer:
1
, the request selected by
The
If bit (
) is
is
If bit
1
is not presented to channel 1; however, the chan-
0
and
and the
, indicating an I/O destination, the following
bit should be set only when both DMA
), which then enables the channel 0 request
) is
and
0
in the
, the
pins.
bit is
channel end
are ).
bit can be written by software
0
, the request signal selected
bit has no effect. When bit
), which subsequently
register is
condition (byte count
or
is
1
1
, indicating
and
is