Z8S18010PEG Zilog, Z8S18010PEG Datasheet - Page 65

• Manufacturer Part Number: Z8S18010PEG
• Description: IC 10MHZ STATIC Z180 64-DIP
• Manufacturer: Zilog

Specifications of Z8S18010PEG

• Processor Type: Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

ZiLOG
The Refresh Control Register (
and length of refresh cycles, while enabling or disabling the
refresh function.
initialized value of
val of 10 clock cycles and be 3 clock cycles in duration.
1. Refresh Cycle insertion is stopped when the CPU is in
2. Refresh cycles are suppressed when the bus is released
the following states:
a. During
b. When the bus is released in response to
c. During
d. During
in response to
continues to operate. The time at which the first
refresh cycle occurs after the Z8S180/Z8L180
reacquires the bus depends on the refresh timer. This
cycle offers no timing relationship with the bus
exchange.
*calculated interval.
states
mode
, refresh cycles occur with an inter-
. However, the refresh timer
After
) specifies the interval
, based on the
fresh controller, while
sertion.
fresh cycle to be two clocks in duration.
the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (
specify the interval (in clock cycles) between refresh cycles.
When dynamic RAM requires 128 refresh cycles every 2
ms (or 256 cycles in every 4 ms), the required refresh in-
terval is less than or equal to 15.625 µs. Thus, the underlined
values indicate the best refresh interval depending on CPU
clock frequency.
3. Refresh cycles are suppressed during
4. The refresh address is incremented by one for each
a refresh cycle is requested during
refresh cycle request is internally latched (until
replaced with the next refresh request). The latched
refresh cycle is inserted at the end of the first machine
cycle after
cycle, the time at which the next refresh cycle occurs
depends on the refresh time and offers no relationship
with the exit from
successful refresh cycle, not for each refresh. Thus,
independent of the number of missed refresh requests,
each refresh bus cycle uses a refresh address
incremented by one from that of the previous refresh
bus cycles.
(see Table 18).
is set to
1
mode is exited. After this initial
).
and
during
mode.
1
is set to
enables refresh cycle in-
are cleared to
.
0
0
1
disables the re-
causes the re-
during
a n d
mode, the
1
0
mode. If
causes
during
.