Z8L18020FSG Zilog, Z8L18020FSG Datasheet - Page 24

• Manufacturer Part Number: Z8L18020FSG
• Description: IC 20MHZ LOW POWER S180 80-QFP
• Manufacturer: Zilog

Specifications of Z8L18020FSG

• Processor Type: Z80
• Features: Enhanced DMA Support
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Processor Series: Z8L18x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

is
Figure 18 indicates the timing of this sequence. The device
takes 64 or 2
ing the bus to an external Master during
when the
As described previously for
the MPU leaves
abled
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
mode due to an external interrupt request that's enabled in
the
While the Z8S180/Z8L180 is in
the bus to an external Master if the
1
.
instruction. If the Z8S180/Z8L180 leaves
–
17
Control Register, but the
(131,072) clock cycles to grant the bus de-
bit in the CPU Control Register (
Low when the
mode due to
and
, flag is
bit (
, bit is
mode, it grants
Low or an en-
modes, when
1
due to an
0
mode,
due to
) is
1
)
.
a
struction(s) following the
or
tion delay, the Z8S180/Z8L180 stays in
Figure 17 indicates the timing for leaving
due to an interrupt request.
pending on the CCR3 bit. The latter (not the
external Masters. If so,
can be used.
instruction, the processor restarts by executing the in-
The Z8S180/Z8L180 takes either 64 or 2
clocks to restart, depending on the CCR3 bit.
goes inactive before the end of the clock stabiliza-
) case may be prohibitive for many demand-driven
instruction. If
or
17
(131,072)
, or
ZiLOG
mode.
mode
mode